System and method for improving isolation in high-density laminated printed circuit boards

• US 9,860,985 B1
• Filed: 12/17/2012
• Issued: 01/02/2018
• Est. Priority Date: 12/17/2012
• Status: Active Grant

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Ajoian, Jack V.
• Primary Examiner(s): Patel, Ishwarbhai B
• Assistant Examiner(s): Paghadal, Paresh
• Application Number:
  US13/716,726
• Time in Patent Office: 1,842 Days
• Field of Search: 174261, 174262, 174264, 174265, 174266, 333 33, 333239, 333242, 333246
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H05K 1/0222 for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/09809 Coaxial layout
• CPC Class Codes: H05K 2201/09854 Hole or via having special cross-section, e.g. elliptical
• CPC Class Codes: H05K 3/3452 Solder masks
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A system and method of isolating a layer-to-layer transition between conductors in a multilayer printed circuit board includes formation of a first ground via at least partially surrounding a first signal conductor in at least one layer of the printed circuit board and formation of a second ground via at least partially surrounding a second signal conductor in another layer of the printed circuit board. The first and second ground vias are plated with a conductive material.

Claims

1. A printed circuit board, comprising:

a plurality of dielectric layers including first, second and third dielectric layers;

a first metal layer arranged on the first dielectric layer, the first metal layer including a first signal conductor arranged on a surface of the first dielectric layer;

a second metal layer arranged between the first dielectric layer and the second dielectric layer;

a second signal conductor arranged between the second dielectric layer and the third dielectric layer;

a via extending through at least a portion of the plurality of dielectric layers and electrically connecting a first end of the first signal conductor to a first end of the second signal conductor;

a first ground via having a C-shaped profile at least partially surrounding the first end of the first signal conductor; and

a second ground via having a C-shaped profile at least partially surrounding the first end of the second signal conductor,

wherein the second ground via extends from the second metal layer through the third dielectric layer.

2. The printed circuit board of claim 1, wherein the first signal conductor comprises a waveguide formed in the first metal layer arranged on the first dielectric layer, and wherein the via extends only from the first end of the first signal conductor to the first end of the second signal conductor.

3. The printed circuit board of claim 2, wherein the first ground via extends from the first metal layer through the first dielectric layer.

4. The printed circuit board of claim 3, wherein the first ground via is electrically connected to the second metal layer.

5. The printed circuit board of claim 1, wherein the second signal conductor comprises a stripline embedded in the plurality of dielectric layers.

6. The printed circuit board of claim 1, wherein the second ground via is electrically connected to a metal layer arranged on a surface of the third dielectric layer opposite the second signal conductor.

7. A printed circuit board, comprising:

a plurality of dielectric layers including first, second and third dielectric layers;

a first signal conductor arranged on a surface of one of the first dielectric layer;

a second signal conductor arranged between the second dielectric layer and the third dielectric layer;

a via extending through at least a portion of the plurality of dielectric layers and electrically connecting a first end of the first signal conductor to a first end of the second signal conductor;

a first ground via at least partially surrounding the first end of the first signal conductor; and

a second ground via at least partially surrounding the first end of the second signal conductor,

wherein the first ground via has a C-shaped profile uniformly extending through a first portion of the plurality of dielectric′

, layers and having first and second free ends connected by a curved portion, and wherein the first and second free ends of the C-shaped first ground via define an opening having a length less than that of the curved portion, and

wherein the second ground via has a C-shaped profile uniformly extending from a metal layer arranged between the first dielectric layer and a second dielectric layer and through the third dielectric layer, and having first and second free ends connected by a curved portion, and wherein the first and second free ends of the C-shaped second ground via define an opening having a length less than that of the curved portion.

8. The printed circuit board of claim 7, wherein the curved portion of each of the C-shaped first ground via and second ground via comprises a constant radius of curvature.

9. The printed circuit board of claim 7, wherein the first and second signal conductors are arranged through the openings of the first ground via and the second ground via, respectively.

10. The printed circuit board of claim 7, wherein the first signal conductor comprises a waveguide defined in a metal layer arranged on the first dielectric layer.

11. The printed circuit board of claim 10, wherein the first ground via extends from the metal layer arranged on the first dielectric layer and though the first dielectric layer.

12. The printed circuit board of claim 11, wherein the first ground via is electrically connected to the metal layer, arranged between the first dielectric layer and a second dielectric′

, layer.

13. The printed circuit board of claim 12, wherein the second signal conductor comprises a stripline embedded in the plurality of dielectric layers.

14. The printed circuit board of claim 7, wherein the second ground via is electrically connected to a metal layer arranged on a surface of the third dielectric layer opposite the second signal conductor.