Temperature compensated reference voltage circuit

• US 9,864,389 B1
• Filed: 11/10/2016
• Issued: 01/09/2018
• Est. Priority Date: 11/10/2016
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Vijaykumar, Sharad
• Primary Examiner(s): Berhane, Adolf
• Application Number:
  US15/348,420
• Time in Patent Office: 425 Days
• Field of Search: 323282, 323284, 323304, 323311-317
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A delta-V_be based bandgap reference voltage circuit generates a temperature stable reference voltage. First and second paths of the circuit each include a respective transistor coupled in series with a resistance. The collector current density of the transistor in first path is lower than the collector current density of transistor in the other path. A control path is used to generate a 2V_be voltage that is coupled to the base nodes of the resistors in each path. A resistance that is coupled between a common node of a first end of the two paths and a circuit ground node. The circuit current is controlled by this resistance and a voltage drop of 2ΔV_be is across the resistance. The output reference voltage of the circuit is 2(V_be+ΔV_be) when stack resistors in each path are used.

Claims

1. A bandgap reference voltage circuit for generating a temperature stable reference voltage output, the circuit comprising:

a plurality of paths, each path comprising a respective transistor coupled in series with a respective resistance, wherein a collector current density of the transistor in a first path of the plurality of paths is less than a collector current density of the respective transistors in other paths of the plurality of paths;

a current setting circuit or element connected to the end of the first path;

an input node of the circuit coupled to a base node of the transistor in the first path;

an output node of the circuit coupled to a base node of the transistor in the second path;

an amplifier circuit coupled between the respective transistors and resistances of each of the plurality of paths; and

a current source coupled to a second end of each path, the current source coupled to and controlled by the amplifier circuit.

2. The circuit of claim 1, wherein each of the plurality of paths comprises a second transistor coupled in series with the transistor of each respective path.

3. The circuit of claim 2, further comprising an input path coupled to the input node, the input path comprising a first transistor coupled in series with a second transistor, each of the first and second transistors having the second area.

4. The circuit of claim 3, wherein each resistance is set in such a way as to control the collector current density of its respective transistor.

5. The circuit of claim 1, wherein the resistances of each path are thin film resistors.

6. The circuit of claim 1, wherein a respective current through each of the plurality of paths is determined by a ratio of the resistances.

7. The circuit of claim 1, wherein the current setting element is a resistor.

8. The circuit of claim 1, wherein base and collector nodes of each respective transistor are coupled together in a diode configuration.

9. The circuit of claim 1, in which at least one prior instance of the bandgap voltage reference circuit is arranged in a cascade with at least one subsequent of the bandgap voltage reference circuit, in which each subsequent instance of the bandgap voltage reference circuit is arranged to output a voltage that offset by 2*Δ

Vbe from its input voltage.

10. The circuit of claim 1, in which N instances of the bandgap voltage reference circuits are arranged in a cascade such that a final output reference voltage is represented by 2(V_be+N*Δ

V_be).

11. A cascaded bandgap reference voltage circuit for generating a temperature stable reference voltage output, the cascaded circuit comprising:

a plurality of delta V_be voltage circuits, each delta V_be voltage circuit comprising;

a plurality of paths, each path comprising a respective transistor coupled in series with a respective resistance, wherein a collector current density of the transistor in a first path of the plurality of paths is lower than a collector current density of transistors in the other paths of the plurality of paths;

a resistance coupled between a reference voltage node and a first end of each path;

an path comprising a transistor having the second area, the input path coupled between the reference voltage node and a base of the transistors of the plurality of paths, an output node of the circuit coupled to the base of the transistors of the plurality of paths;

an amplifier circuit coupled between the respective transistors and resistances of each of the plurality of paths; and

a current source coupled to a second end of each path, the current source coupled to and controlled by the operational amplifier; and

a voltage curvature correction circuit coupled to the plurality of bandgap reference voltage circuits and configured to generate a curvature corrected reference voltage.

12. The cascaded circuit of claim 11, wherein the voltage curvature correction circuit comprises:

first and second paths, each path comprising a respective transistor and each transistor having a respective area, each transistor coupled in series with a respective resistance, wherein a collector current density of the transistor in the first path is lower than the collector current density of the transistor in the second path;

a first current source coupled between a common node of a first end of the first and second paths and a ground reference node;

an amplifier circuit coupled between the respective transistors and resistances of each of the first and second paths; and

a second current source coupled to a common node of a second end of the first and second paths, the second current source coupled to and controlled by the amplifier circuit; and

a third path coupled between the transistor and resistance of the second path and the common node of the second end;

wherein the first path comprises a first current, the second path comprise a second current, and the third path comprises a third current.

13. The cascaded circuit of claim 12, wherein the first current is an I_ZTAT (zero to absolute temperature) current, the second current is a I_PTAT (proportional to absolute temperature) current, and the third current is a I_CTAT (complementary to absolute temperature) current.

14. The cascaded circuit of claim 13, wherein the first current source has a current equal to I_ZTAT.

15. The cascaded circuit of claim 14, wherein the first current source comprises a resistance in series with a transistor.

16. The cascaded circuit of claim 11, further comprising a capacitance coupled in parallel with the resistance of the first path.

17. The cascaded circuit of claim 11, in which each instance in the cascade is configured to output a voltage that is offset by 2*Δ

Vbe from its input voltage.

18. The cascaded circuit of claim 11, in which N instances of the bandgap voltage reference circuits are arranged in the cascade such that a final output reference voltage is represented by 2(V_be+N*Δ

V_be).

19. A method for generating a temperature stable reference voltage in a reference voltage circuit, the method comprising:

generating a first current in a first path comprising a first transistor having a first collector current density;

generating a second current in a second path comprising a second transistor having a second collector current density, wherein the first collector current density is less than the second collector current density;

generating a control voltage that is coupled to a base node of the first and second transistors;

controlling a current through the reference voltage circuit based on a resistance between a common node of the first and second paths and a ground node, the resistance having a delta voltage between the common node and the ground node; and

outputting the reference voltage that is a sum of the control voltage and the delta voltage.

20. The method of claim 19, further comprising correcting a curvature of the reference voltage.

21. The method of claim 20, wherein correcting the curvature of the reference voltage comprises adding a correction voltage to the reference voltage.

22. The method of claim 21, wherein the correction voltage is a substantially inverse voltage from the reference voltage.

23. The method of claim 19, wherein the output reference voltage is represented by 2(V_be+Δ

V_be), wherein 2V_be is a base-to-emitter voltage of two bipolar junction transistors coupled in series and 2Δ

V_be is the delta voltage.

24. The method of claim 23, further comprising adding the reference voltage output of each of N reference voltage circuits that are cascaded such that a final output reference voltage is represented by 2(V_be+N*Δ

V_be).