Methods for configurable hardware logic device reloading and devices thereof

• US 9,864,606 B2
• Filed: 09/03/2014
• Issued: 01/09/2018
• Est. Priority Date: 09/05/2013
• Status: Active Grant

• Current Assignee: F5 Networks, Inc. (F5 Incorporated)
• Original Assignee: F5 Networks, Inc. (F5 Incorporated)
• Inventors: Mimms, Alan B., Troksa, Tom
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Neveln, Joshua
• Application Number:
  US14/476,424
• Publication Number:
  US 20150121060A1
• Time in Patent Office: 1,224 Days
• Field of Search: None
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/441 Multiboot arrangements, i.e. selecting an operating system to be loaded
• CPC Class Codes: G06F 9/4413 Plug-and-play [PnP]

Abstract

A method and host computing device that restricts access by one or more applications to a configurable hardware logic device over a bus. At least a portion of the configurable hardware logic device is reconfigured. A determination is made when unplug and plug events have been generated by the configurable hardware logic device. The unplug and plug events are generated without disconnecting power supplied to the configurable hardware logic device. The configurable hardware logic device is re-enumerated on the bus when the determining indicates the unplug and plug events have been generated by the configurable hardware logic device.

Claims

1. A method for configurable hardware logic device reloading implemented by a host computing system comprising one or more host computing apparatuses, client devices or server devices, the method comprising:

identifying a new configuration to be loaded for a configurable hardware logic device, wherein the new configuration is received by the configurable hardware logic device using a first bus;

restricting access by one or more applications to the configurable hardware logic device over a second bus, upon identifying the new configuration is to be loaded for the configurable hardware logic device;

reconfiguring at least a portion of the configurable hardware logic device;

determining when unplug and plug events have been generated by the configurable hardware logic device, wherein the unplug and plug events are generated without disconnecting power supplied to the configurable hardware logic device and the unplug and plug events are received using the second bus;

re-enumerating the configurable hardware logic device on the bus, when the unplug and plug events are determined to have been generated by the configurable hardware logic device; and

allowing the restricted one or more applications to communicate with the configurable hardware logic device, subsequent to the re-enumeration of the configurable hardware logic device.

2. The method as set forth in claim 1 wherein the unplug and plug events are warm events generated sequentially:

and

waiting for the unplug and plug events to be generated by the configurable hardware logic device, when it is determined that the unplug and plug events have not been generated.

3. The method as set forth in claim 1 wherein the reconfiguring further comprises partial reloading the configurable hardware logic device with a bit file using the first bus;

and

wherein the partial reloading further comprises maintaining a portion of the configurable hardware logic device that is configured to receive data from the second bus.

4. The method as set forth in claim 1 wherein the configurable hardware logic device is connected to the first bus at a port and the restricting further comprises disabling the port;

and

wherein the reconfiguring further comprises reconfiguring the at least a portion of the configurable hardware logic device using the second bus.

5. The method as set forth in claim 1 wherein the configurable hardware logic device is reconfigured at least in part to cause the configurable hardware logic device to autonomously generate the plug event.

6. A host computing apparatus, comprising a memory comprising programmed instructions stored thereon and one or more processors configured to be capable of executing the stored programmed instructions to:

identify a new configuration to be loaded for a configurable hardware logic device, wherein the new configuration is received by the configurable hardware logic device using a first bus;

restrict access by one or more applications to the configurable hardware logic device over a second bus, upon identifying the new configuration is to be loaded for the configurable hardware logic device;

reconfigure at least a portion of the configurable hardware logic device;

determine when unplug and plug events have been generated by the configurable hardware logic device, wherein the unplug and plug events are generated without disconnecting power supplied to the configurable hardware logic device and the unplug and plug events are received using the second bus;

re-enumerate the configurable hardware logic device on the bus, when the unplug and plug events are determined to have been generated by the configurable hardware logic device; and

allow the restricted one or more applications to communicate with the configurable hardware logic device, subsequent to the re-enumeration of the configurable hardware logic device.

7. The apparatus as set forth in claim 6 wherein the unplug and plug events are warm events generated sequentially;

and

wait for the unplug and plug events to be generated by the configurable hardware logic device, when it is determined that the unplug and plug events have not been generated.

8. The apparatus as set forth in claim 6 wherein the wherein the one or more processors are further configured to be capable of executing the stored programmed instructions to partially reload the configurable hardware logic device with a bit file using the first bus;

and

wherein the partial reloading further comprises maintaining a portion of the configurable hardware logic device that is configured to receive data from the second bus.

9. The apparatus as set forth in claim 6 wherein the configurable hardware logic device is connected to the first bus at a port and the restricting further comprises disabling the port;

and

wherein the reconfiguring further comprises reconfiguring the at least a portion of the configurable hardware logic device using the second bus.

10. The apparatus as set forth in claim 6 wherein the configurable hardware logic device is reconfigured at least in part to cause the configurable hardware logic device to autonomously generate the plug event.

11. A non-transitory computer readable medium having stored thereon instructions for configurable hardware logic device reloading comprising executable code which when executed by one or more processors, causes the one or more processors to:

identify a new configuration to be loaded for a configurable hardware logic device, wherein the new configuration is received by the configurable hardware logic device using a first bus;

restrict access by one or more applications to the configurable hardware logic device over a second bus, upon identifying the new configuration is to be loaded for the configurable hardware logic device;

reconfigure at least a portion of the configurable hardware logic device;

determine when unplug and plug events have been generated by the configurable hardware logic device, wherein the unplug and plug events are generated without disconnecting power supplied to the configurable hardware logic device and the unplug and plug events are received using the second bus;

re-enumerate the configurable hardware logic device on the bus, when the unplug and plug events are determined to have been generated by the configurable hardware logic device; and

allow the restricted one or more applications to communicate with the configurable hardware logic device, subsequent to the re-enumeration of the configurable hardware logic device.

12. The non-transitory computer readable medium as set forth in claim 11 wherein the unplug and plug events are warm events generated sequentially;

and

wait for the unplug and plug events to be generated by the configurable hardware logic device, when it is determined that the unplug and plug events have not been generated.

13. The non-transitory computer readable medium as set forth in claim 11 wherein the executable code when executed by the one or more processors further causes the one or more processors to partially reload the configurable hardware logic device with a bit file using the first bus;

and

wherein the partial reloading further comprises maintaining a portion of the configurable hardware logic device that is configured to receive data from the second bus.

14. The non-transitory computer readable medium as set forth in claim 11 wherein the configurable hardware logic device is connected to the first bus at a port and the restricting further comprises disabling the port;

and

wherein the reconfiguring further comprises reconfiguring the at least a portion of the configurable hardware logic device using the second bus.

15. The non-transitory computer readable medium as set forth in claim 11 wherein the configurable hardware logic device is reconfigured at least in part to cause the configurable hardware logic device to autonomously generate the plug event.

16. A host computing system, comprising one or more host computing apparatuses, or server devices, the host computing system comprising memory comprising programmed instructions stored thereon and one or more processors configured to be capable of executing the stored programmed instructions to:

identify a new configuration to be loaded for a configurable hardware logic device, wherein the new configuration is received by the configurable hardware logic device using a first bus;

restrict access by one or more applications to the configurable hardware logic device over a second bus, upon identifying the new configuration is to be loaded for the configurable hardware logic device;

reconfigure at least a portion of the configurable hardware logic device;

determine when unplug and plug events have been generated by the configurable hardware logic device, wherein the unplug and plug events are generated without disconnecting power supplied to the configurable hardware logic device and the unplug and plug events are received using the second bus;

re-enumerate the configurable hardware logic device on the bus, when the unplug and plug events are determined to have been generated by the configurable hardware logic device; and

allow the restricted one or more applications to communicate with the configurable hardware logic device, subsequent to the re-enumeration of the configurable hardware logic device.

17. The host computing system as set forth in claim 16 wherein the unplug and plug events are warm events generated sequentially;

and

wait for the unplug and plug events to be generated by the configurable hardware logic device, when it is determined that the unplug and plug events have not been generated.

18. The host computing system as set forth in claim 16 wherein the one or more processors are further configured to be capable of executing the stored programmed instructions to partially reload the configurable hardware logic device with a bit file using the first bus;

and

wherein the partial reloading further comprises maintaining a portion of the configurable hardware logic device that is configured to receive data from the second bus.

19. The host computing system as set forth in claim 16 wherein the configurable hardware logic device is connected to the first bus at a port and the restricting further comprises disabling the port;

and

wherein the reconfiguring further comprises reconfiguring the at least a portion of the configurable hardware logic device using the second bus.

20. The host computing system as set forth in claim 16 wherein the configurable hardware logic device is reconfigured at least in part to cause the configurable hardware logic device to autonomously generate the plug event.