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Memory having a static cache and a dynamic cache

  • US 9,864,697 B2
  • Filed: 05/30/2017
  • Issued: 01/09/2018
  • Est. Priority Date: 06/10/2015
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory, wherein the memory includes;

    a first portion configured to operate as a static single level cell (SLC) cache; and

    a second portion configured to operate as a dynamic SLC cache or multilevel cell (MLC) memory based on whether a quantity of erase operations performed on the second portion of the memory meets or exceeds a particular threshold.

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