Memory having a static cache and a dynamic cache

• US 9,864,697 B2
• Filed: 05/30/2017
• Issued: 01/09/2018
• Est. Priority Date: 06/10/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hale, Christopher S., Ratnam, Sampath K., Muchherla, Kishore K.
• Primary Examiner(s): Lane, John A
• Application Number:
  US15/607,715
• Publication Number:
  US 20170262376A1
• Time in Patent Office: 224 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Claims

1. An apparatus, comprising:

a memory, wherein the memory includes;

a first portion configured to operate as a static single level cell (SLC) cache; and

a second portion configured to operate as a dynamic SLC cache or multilevel cell (MLC) memory based on whether a quantity of erase operations performed on the second portion of the memory meets or exceeds a particular threshold.

2. The apparatus of claim 1, wherein the second portion of the memory is configured to operate as MLC memory upon the quantity of erase operations performed on the second portion of the memory meeting or exceeding the particular threshold.

3. The apparatus of claim 1, wherein the second portion of the memory is configured to operate as a dynamic SLC cache or MLC memory based on whether a quantity program operations performed on the second portion of the memory meets or exceeds a particular threshold.

4. The apparatus of claim 1, wherein the second portion of the memory is configured to operate as a dynamic SLC cache or MLC memory based on whether the entire first portion of the memory has data stored therein.

5. The apparatus of claim 1, wherein:

the memory comprises a plurality of blocks of memory cells;

the first portion of the memory comprises a first number of the plurality of blocks; and

the second portion of the memory comprises a second number of the plurality of blocks.

6. The apparatus of claim 5, wherein the first number of the plurality of blocks is smaller than the second number of the plurality of blocks.

7. A method of operating memory, comprising:

configuring a first portion of a memory to operate as a static single level cell (SLC) cache; and

configuring a second portion of the memory to operate as a dynamic SLC cache or multilevel cell (MLC) memory based on whether a quantity of blocks of memory cells in the second portion of the memory having data stored therein meets or exceeds a particular threshold.

8. The method of claim 7, wherein the method includes configuring the second portion of the memory to operate as MLC memory upon the quantity of blocks of memory cells in the second portion of the memory having data stored therein meeting or exceeding the particular threshold.

9. The method of claim 8, wherein the method includes programming data stored in the first portion of the memory to the second portion of the memory upon configuring the second portion of the memory to operate as MLC memory.

10. The method of claim 8, wherein the method includes programming data received in a command from a host to the first portion of the memory upon configuring the second portion of the memory to operate as MLC memory.

11. The method of claim 7, wherein the method includes programming data to the first portion of the memory or the second portion of the memory based on whether the entire first portion of the memory has data stored therein.

12. The method of claim 11, wherein the method includes programming the data to the second portion of the memory upon the entire first portion of the memory having data stored therein.

13. The method of claim 7, wherein the method includes:

configuring the first portion of the memory to operate as a static SLC cache using a controller of the memory; and

configuring the second portion of the memory to operate as a dynamic SLC cache or MLC memory using the controller of the memory.

14. The method of claim 7, wherein configuring the first portion of the memory to operate as a static SLC cache includes configuring the first portion of the memory to operate as a dedicated cache in SLC mode.

15. The method of claim 7, wherein configuring the second portion of the memory to operate as a dynamic SLC cache includes configuring the second portion of the memory to operate as an overflow cache in SLC mode.

16. An apparatus, comprising:

a memory, wherein the memory includes;

a first portion configured to operate as a static single level cell (SLC) cache; and

a second portion configured to operate as a dynamic SLC cache or multilevel cell (MLC) memory based on whether a quantity of blocks of memory cells used by the memory to program data stored in single level cells of the memory to multilevel cells of the memory is equal to or greater than a quantity of blocks of memory cells in the second portion of the memory.

17. The apparatus of claim 16, wherein the second portion of the memory is configured to operate as MLC memory upon the quantity of blocks of memory cells used by the memory to program data stored in single level cells of the memory to multilevel cells of the memory being equal to or greater than the quantity of blocks of memory cells in the second portion of the memory.

18. The apparatus of claim 16, wherein a size of the second portion of the memory corresponds to the quantity of blocks of memory cells used by the memory to program data stored in single level cells of the memory to multilevel cells of the memory.

19. The apparatus of claim 16, wherein the memory includes a third portion configured to operate as MLC memory.

20. The apparatus of claim 19, wherein:

the first portion of the memory is configured to operate as the static SLC cache for an entire lifetime of the memory; and

the third portion of the memory is configured to operate as MLC memory for the entire lifetime of the memory.