Memory device including current generator plate

• US 9,865,311 B1
• Filed: 07/08/2016
• Issued: 01/09/2018
• Est. Priority Date: 07/08/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/205,640
• Publication Number:
  US 20180012634A1
• Time in Patent Office: 550 Days
• Field of Search: 36518518
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second conductive material located in a second level of the apparatus; pillars extending between the first and second levels and contacting the first and second conductive materials; memory cells located along the pillars; first select gates located in a third level of the apparatus between the first and second levels, with each of the first select gates being located along a segment of a respective pillar among the pillars; second select gates located in a fourth level of the apparatus between the first and third levels; and a conductive plate located in a fifth level of the apparatus between the first and fourth levels, with each of the pillars extending through the conductive plate.

Claims

1. An apparatus comprising:

a first conductive material located in a first level of the apparatus;

a second conductive material located in a second level of the apparatus;

pillars extending between the first and second levels and contacting the first and second conductive materials;

memory cells located along the pillars;

first select gates located in a third level of the apparatus between the first and second levels, each of the first select gates including a first piece of material located along a first segment of a respective pillar among the pillars;

second select gates located in a fourth level of the apparatus between the first and third levels, each of the second select gates including a second piece of material located in the fourth level of the apparatus between the first and third levels; and

a conductive plate including a third piece of material, located in a fifth level of the apparatus between the first and fourth levels, each of the pillars extending through the conductive plate, wherein the third piece of material is separated from each of the first and second pieces of materials by a dielectric.

2. The apparatus of claim 1, wherein the conductive plate a polycrystalline silicon plate.

3. The apparatus of claim 1, further comprising a substrate, wherein the first and second select gates are between the conductive plate and the substrate.

4. The apparatus of claim 1, further comprising a substrate, wherein the conductive plate is between the substrate and the first and second select gates.

5. The apparatus of claim 1, further comprising select lines coupled to the first select gates, wherein the conductive plate has a thickness greater than a thickness of each of the select lines.

9. The apparatus of claim 1, wherein apparatus comprises a memory device, the memory device comprising:

a substrate;

data lines over the substrate; and

a plurality of conductive plates between the substrate and the data lines, the plurality of conductive plates being located immediately next to the data lines, wherein the first material is included in one of the data lines, and the conductive plate is included in the plurality of conductive plates.

10. The apparatus of claim 1, wherein the apparatus comprises a memory device, the memory device comprising:

a substrate; and

a first deck and a second deck arranged vertically over the first deck and the substrate, the first deck including the first conductive material, the second conductive material, the pillars, the memory cells, the first select gates, the second select gates, and the conductive plate, and the second deck including additional memory cells.

6. An apparatus comprising:

a first conductive material located in a first level of the apparatus;

a second conductive material located in a second level of the apparatus;

pillars extending between the first and second levels and contacting the first and second conductive materials;

memory cells located along the pillars;

first select gates located in a third level of the apparatus between the first and second levels, each of the first select gates being located along a segment of a respective pillar among the pillars;

second select gates located in a fourth level of the apparatus between the first and third levels;

a conductive plate located in a fifth level of the apparatus between the first and fourth levels each of the pillars extending through the conductive plate; and

select lines coupled to the first select gates, wherein the conductive plate has a thickness greater than a thickness of each of the select lines, wherein the conductive plate and each of the select lines have different materials.

7. An apparatus comprising:

a first conductive material located in a first level of the apparatus;

a second conductive material located in a second level of the apparatus;

pillars extending between the first and second levels ting the first and second conductive materials;

memory cells located along the pillars;

first select gates located in a third level of the apparatus between the first and second levels, each of the first select gates being located along a segment of a respective pillar among the pillars;

second select gates located in a fourth level of the apparatus between the first and third levels;

a conductive plate located in a fifth level of the apparatus between the first and fourth levels, each of the pillars extending through the conductive plate; and

select lines coupled to the first select gates, wherein the conductive plate has a thickness greater than a thickness of each of the select lines, wherein the conductive plate is a polycrystalline silicon plate, and each of the select lines is a metal select line.

8. The apparatus of claim 7, further comprising control lines coupled to the memory cells, wherein each of the control lines is a metal control line.

11. A method comprising:

forming a pillar extending between a data line source, the pillar including a first segment, a second segment, a third segment, and a fourth segment, the second segment being between the first and third segments, and the third segment being between the second and fourth segments;

forming a memory cell string and control lines along the fourth segment of the pillar;

forming a first select gate including forming a first piece of material along the second segment of the pillar;

forming a second select gate including forming a second piece of material along the third segment of the pillar;

forming a conductive plate including forming a third piece of material in a level of the memory device between the data line and the source, wherein the third piece of material is separated from each of the first and second pieces of materials by a dielectric; and

forming a dielectric between a portion of the conductive plate and the first segment of the pillar.

12. The method of claim 11, wherein the conductive plate is formed after the first and second select gates are formed.

13. The method of claim 11, wherein the conductive plate is formed before the first and second select gates are formed.

14. The method of claim 11, wherein the conductive plate and the control lines are formed from different materials.

15. The method of claim 11, wherein conductive plate is from polycrystalline silicon and the control lines are formed from metal.