Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

• US 9,865,332 B2
• Filed: 01/20/2016
• Issued: 01/09/2018
• Est. Priority Date: 04/10/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US15/002,207
• Publication Number:
  US 20160148675A1
• Time in Patent Office: 720 Days
• Field of Search: None
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/337 Design optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Claims

1. A method of operating a multi-transistor, scalable SRAM cell having a single floating body transistor, said method comprising:

providing the floating body transistor in which ground is applied to a source of the floating body transistor, and wherein said source comprises a first conductivity type selected from p-type and n-type conductivity types, and in which a drain of the floating body transistor comprising a second conductivity type selected from said p-type and n-type conductivity types and different from said first conductivity type is connected to a write access transistor and a read sense device,

wherein said floating body transistor comprises a floating body region configured to be charged to a level indicative of a state of the memory cell;

a buried layer having a different conductivity type from a conductivity type of said floating body region;

biasing said buried layer to ensure bistable operation of the floating body transistor; and

applying pure logic levels on a bit line connected to said write access transistor and a read access transistor in combination with operation of a write word line and a read word line connected to said write access transistor and said read access transistor, respectively.

2. The method of claim 1, comprising performing a read operation, wherein said applying pure logic levels comprises pre-charging the bit line to a high voltage and said read operation comprises driving the read word line high;

and

sensing a state of the floating body transistor via the read access transistor when the read word line has been driven high.

3. The method of claim 1, comprising performing a write operation, wherein said applying pure logic levels comprises driving a desired state voltage to the bit line.

4. A method of operating a multi-transistor, scalable SRAM cell having a single floating body transistor, said method comprising:

providing the floating body transistor in which ground is applied to a source region of the floating body transistor and a write bit line that is separate from and independently operable of a read bit line, wherein the read bit line is connected to a read access transistor, the write bit line is connected to a write access transistor, and a read sense device is connected between the read access transistor and the floating body transistor; and

applying pure logic levels on one or both of the write bit line and the read bit line;

wherein said floating body transistor comprises

a floating body having a first conductivity type selected from p-type and n-type conductivity types,

said source region comprising a second conductivity type selected from said p-type and n-type conductivity types and different from said first conductivity type,

a drain region comprising said first conductivity type, and

a buried layer bounding said floating body comprising said second conductivity type, wherein said buried layer configured to be biased to ensure bistable operation of the floating body transistor.

5. The method of claim 4, wherein independent paths for read and write are provided, such that a dual port operation is possible wherein one write operation and one read operation are applied to the SRAM cell simultaneously.

6. The method of claim 4, further comprising providing additional peripheral logic to implement, cache and arbitrate two simultaneous read or two simultaneous write operations to fully emulate a dual port cell.

7. A method of operating a multi-transistor, scalable SRAM cell having a single floating body transistor, said method comprising:

providing the floating body transistor in which two [P+] contacts having a first conductivity type selected from p-type and n-type conductivity types are provided and a region having a second conductivity type selected from said p-type and n-type conductivity types and different from said first conductivity type is connected to ground;

wherein one of two contacts having said first conductivity type is connected to a write access transistor connected to a write select line, wherein said write select line must be enabled to perform a write operation; and

applying pure logic levels on at least one bit line connected to one of said write access transistor and a read access transistor in combination with operation of at least one of a write word line connected to the floating body transistor and a read word line connected to said read access transistor;

wherein said floating body transistor comprises a floating body and a buried layer bounding said floating body, said buried layer configured to be biased to ensure bistable operation of the floating body transistor.

8. The method of claim 7, wherein said floating body transistor includes a dual gate structure.

9. The method of claim 7, wherein the write select line is shared across multiple SRAM cells.