Memory system with non-volatile memory device that is capable of single or simulataneous multiple word line selection

• US 9,865,351 B2
• Filed: 06/07/2016
• Issued: 01/09/2018
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Maejima, Hiroshi
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Ojha, Ajay
• Application Number:
  US15/175,772
• Publication Number:
  US 20170075595A1
• Time in Patent Office: 581 Days
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A memory system includes a memory device including a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells, and a controller configured to control an operation of the memory device. The memory device selects one word line when reading from or writing to the first memory cells and selects more than one word line when reading from or writing to the second memory cells.

Claims

1. A memory system comprising:

a memory device that includes

a memory cell array having a plurality of memory string units including a first memory string unit and a second memory string unit, each of the memory string units including a plurality of memory strings, each memory string having a first transistor, a second transistor, and a plurality of memory cells connected between the first transistor and the second transistor, the plurality of memory cells including a first memory cell and a second memory cell,

a first word line connected to gates of the first memory cells in the first and second memory string units,

a second word line connected to gates of the second memory cells in the first and second memory string units,

a first select gate line connected to the first transistors in the first memory string unit, and

a second select gate line connected to the first transistors in the second memory string unit; and

a controller configured to control an operation of the memory device,

wherein during reading from or writing to the first memory string unit, the memory device selects the first select gate line, does not select the second select gate line, and while the first select gate line is selected and the second select gate line is not selected, simultaneously reads from or writes to the first and second memory cells in the memory strings of the first memory string unit.

2. The system according to claim 1, wherein the memory device selects the first and second word lines during the reading from or writing to the first memory string unit.

3. The system according to claim 2, wherein the first and second word lines are adjacent word lines.

4. The system according to claim 1, wherein the first memory cells and the second memory cells are single-level cells and one page of data is read or written with the selection of first and second word lines.

11. The system according to claim 1 wherein when the memory device reads from or write to the first and second memory cells in the first memory string unit, the memory device does not read from or write to the first and second memory cells in the second memory string unit.

12. The system according to claim 1, wherein the memory device further includes:

a bit line connected to a first memory string, which is one of the memory strings of the first memory string unit, and a second memory string, which is one of the memory strings in the second memory string unit.

13. The system according to claim 1, wherein

the memory device is configured to divide the memory cell array into a first region and a second region, the first memory string unit and the second memory string unit belonging to the first region, and

the plurality of memory string units further includes a third memory string unit belonging to the second region, wherein the memory device selects a word line one at a time when reading from or writing to the memory cells in the third memory string unit.

14. The system according to claim 13,

wherein the controller transmits a read or write command with a first control signal indicating that a read or write target is in the first region, and transmits the read or write command without the first control signal if the read or write target is in the second region.

15. The system according to claim 13,

wherein the first region stores a read voltage and a shift read voltage to be used when reading from a read or write target that is in the first region and a programming voltage to be used when writing to the read or write target that is in the first region.

16. The system according to claim 13, wherein the controller is configured to maintain access frequency information of a page of data stored in the second region and to transfer the page of data stored in the second region to the first region based on the access frequency.

17. The system according to claim 16, wherein the controller instructs the memory device to transfer the page of data stored in the second region to the first region when the controller determines that the access frequency of the page of data is below a threshold.

18. The system according to claim 17, wherein the controller maps the page of data to an address within the first region upon receiving confirmation from the memory device that the transfer has completed.

5. A method of performing a reading operation in a memory device that includes

a memory cell array having a plurality of memory string units including a first memory string unit and a second memory string unit, each of the memory string units including a plurality of memory strings, each memory string having a first transistor, a second transistor, and a plurality of memory cells connected between the first transistor and the second transistor, the plurality of memory cells including a first memory cell and a second memory cell,

a first word line connected to gates of the first memory cells in the first and second memory string units,

a second word line connected to gates of the second memory cells in the first and second memory string units,

a first select gate line connected to the first transistors in the first memory string unit, and

a second select gate line connected to the first transistors in the second memory string unit,

said method comprising:

upon receiving a command to read from the first memory string unit, selecting the first select gate line and not selecting the second select gate line, and while the first select gate line is selected and the second select gate line is not selected, applying a first read voltage to the first and second word lines at the same time.

6. The method according to claim 5, wherein the first and second word lines are adjacent word lines.

7. The method according to claim 5, wherein the first memory cells and the second memory cells are single-level cells and one page of data is read with the selection of first and second word lines.

19. The method according to claim 5, wherein

the memory device is configured to divide the memory cell array into a first region and a second region and to read the first read voltage from the first region, the first memory string unit and the second memory string unit belonging to the first region, and

the plurality of memory string units further includes a third memory string unit belonging to the second region, wherein the memory device selects a word line one at a time when reading from the memory cells in the third memory string unit.

8. A method of performing a writing operation in a memory device that includes

a memory cell array having a plurality of memory string units including a first memory string unit and a second memory string unit, each of the memory string units including a plurality of memory strings, each memory string having a first transistor, a second transistor, and a plurality of memory cells connected between the first transistor and the second transistor, the plurality of memory cells including a first memory cell and a second memory cell,

a first word line connected to gates of the first memory cells in the first and second memory string units,

a second word line connected to gates of the second memory cells in the first and second memory string units,

a first select gate line connected to the first transistors in the first memory string unit, and

a second select gate line connected to the first transistors in the second memory string unit,

said method comprising:

upon receiving a command to write to the first memory string unit, selecting the first select gate line and not selecting the second select gate line, and while the first select gate line is selected and the second select gate line is not selected, applying a first programming voltage to the first and second word lines at the same time.

9. The method according to claim 8, wherein the first and second word lines are adjacent word lines.

10. The method according to claim 8, wherein the first memory cells and the second memory cells are single-level cells and one page of data is written with the selection of first and second word lines.

20. The method according to claim 8, wherein

the memory device is configured to divide the memory cell array into a first region and a second region and to read the first programming voltage from the first region, the first memory string unit and the second memory string unit belonging to the first region, and

the plurality of memory string units further includes a third memory string unit belonging to the second region, wherein the memory device selects a word line one at a time when writing to the memory cells in the third memory string unit.