Methods of forming conductive and insulating layers

• US 9,865,575 B2
• Filed: 07/05/2016
• Issued: 01/09/2018
• Est. Priority Date: 06/27/2013
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Chi, HeeJo, Shin, HanGil, Kim, KyungMoon
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US15/202,349
• Publication Number:
  US 20160329310A1
• Time in Patent Office: 553 Days
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/831 the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.

Claims

1. A method of making a semiconductor device, comprising:

providing a substrate;

disposing a semiconductor die over the substrate;

depositing an encapsulant around the semiconductor die;

forming an insulating material over a portion of the encapsulant and a portion of the semiconductor die using an inkjet printing process; and

forming a first conductive layer over the insulating material, wherein a portion of the first conductive layer over the semiconductor die is contained completely within a footprint of the insulating material.

2. The method of claim 1, further including forming an interconnect structure over the substrate adjacent to the semiconductor die.

3. The method of claim 1, wherein forming the insulating material includes:

depositing the insulating material in a viscous state; and

heating the insulating material from the viscous state to a non-viscous state.

4. The method of claim 1, wherein the insulating material includes dielectric ink, dielectric paste, or thermosetting resin.

5. The method of claim 1, further including forming a second conductive layer over the first conductive layer.

6. The method of claim 1, further including forming an insulating layer over the first conductive layer.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around the semiconductor die, wherein an upper surface of the semiconductor die is exposed from the encapsulant;

printing an insulating material over the upper surface of the semiconductor die; and

forming a first conductive layer over the insulating material, wherein the insulating material electrically isolates the first conductive layer from the upper surface of the semiconductor die.

8. The method of claim 7, further including:

providing a substrate, wherein the semiconductor die is disposed over the substrate; and

forming an interconnect structure over the substrate adjacent to the semiconductor die.

9. The method of claim 7, wherein forming the insulating material includes:

depositing the insulating material in a viscous state; and

heating the insulating material from the viscous state to a non-viscous second state.

10. The method of claim 7, wherein the insulating material includes dielectric ink, dielectric paste, or thermosetting resin.

11. The method of claim 7, further including printing the first conductive layer over the insulating material.

12. The method of claim 7, further including forming a second conductive layer over the first conductive layer.

13. The method of claim 7, further including forming an insulating layer over the first conductive layer.

14. A semiconductor device, comprising:

a substrate;

a semiconductor die disposed over the substrate;

an encapsulant deposited around the semiconductor die;

an insulating print material formed over the semiconductor die; and

a first conductive layer including a contact pad formed over the insulating print material within a footprint of the semiconductor die, wherein the first conductive layer is electrically isolated from the semiconductor die by the insulating print material.

15. The semiconductor device of claim 14, further including an interconnect structure formed over the substrate adjacent to the semiconductor die.

16. The semiconductor device of claim 14, wherein the insulating print material includes dielectric ink, dielectric paste, or thermosetting resin.

17. The semiconductor device of claim 14, wherein the first conductive layer includes conductive ink or conductive liquid.

18. The semiconductor device of claim 14, further including a second conductive layer formed over the first conductive layer.

19. The semiconductor device of claim 14, further including an insulating layer formed over the first conductive layer.

20. A semiconductor device, comprising:

a semiconductor die;

an encapsulant deposited around the semiconductor die;

an insulating print material on the semiconductor die; and

a first conductive layer formed on the insulating print material, wherein the first conductive layer contacts the encapsulant outside a footprint of the semiconductor die and the first conductive layer is physically separated from the semiconductor die by the insulating print material.

21. The semiconductor device of claim 20, further including:

a substrate, wherein the semiconductor die is disposed over the substrate; and

an interconnect structure formed over the substrate adjacent to the semiconductor die.

22. The semiconductor device of claim 20, wherein the insulating print material includes dielectric ink, dielectric paste, or thermosetting resin.

23. The semiconductor device of claim 20, wherein the first conductive layer includes conductive ink or conductive liquid.

24. The semiconductor device of claim 20, further including a second conductive layer formed over the first conductive layer.

25. The semiconductor device of claim 20, further including an insulating layer formed over the first conductive layer.