Low power semiconductor transistor structure and method of fabrication thereof

• US 9,865,596 B2
• Filed: 09/21/2016
• Issued: 01/09/2018
• Est. Priority Date: 04/12/2010
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Shifren, Lucian, Ranade, Pushkar, Thompson, Scott E., Sonkusale, Sachin R., Zhang, Weimin
• Primary Examiner(s): Li, Meiya
• Application Number:
  US15/272,113
• Publication Number:
  US 20170012044A1
• Time in Patent Office: 475 Days
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV_T compared to conventional bulk CMOS and can allow the threshold voltage V_T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Claims

1. An integrated circuit having transistor devices of a plurality of device types formed on a substrate, comprising:

a first screening layer for a first device type, the first screening layer being positioned below a first gate insulator of the first device type, the first screening layer haying a first dopant concentration;

a second screening layer for a second device type, the second screening layer being positioned below a second gate insulator of the second device type, the second screening layer having a second dopant concentration;

a threshold voltage layer for a third device type, the threshold voltage layer being positioned below a third gate insulator of the third device type, the threshold voltage layer having a third dopant concentration;

a first substantially undoped layer for the first device type being positioned above and adjacent to the first screening layer;

a second substantially undoped layer for the second device type being positioned above and adjacent to the second screening layer,

a shallow trench isolation isolating the first device type, the second device type and the third device type;

a first source and drain region for the first device type penetrating the first substantially undoped layer and the first screening layer;

a second source and drain region for the second device type penetrating the second substantially undoped layer and the second screening layer,

wherein a thickness of the first gate insulator is different from a thickness of the second gate insulator and a depth position of the threshold voltage layer is different from each of a depth of position of the first screening layer and the second screening layer.

2. The integrated circuit of claim 1, wherein the first screening layer for the first device type further includes a first P-type screening layer for a first transistor element of the first device type, and a first N-type screening layer for a second transistor element of the first device type.

3. The integrated circuit of claim 1, further comprising:

a body tap operable to apply a body bias voltage to a body of the first transistor element of the first device type.

4. The integrated circuit of claim 1, wherein the second screening layer for the second device type further includes a second P-type screening layer for a first transistor element of the second device type, and a second N-type screening layer for a second transistor element of the second device type.

5. The integrated circuit of claim 1, further comprising:

a body tap operable to apply a bias voltage to a body of the first transistor element of the second device type.

6. The integrated circuit of claim 1, further comprising:

one of a single, double, or triple gate oxidation layers for each device.

7. The integrated circuit of claim 1, wherein a thickness of the first substantially undoped layer is same to a thickness of the second substantially undoped layer.

8. The integrated circuit of claim 1, further comprising:

a first Lightly Doped Drain (LDD) for the first device type and a second LDD for the second device type, a depth position of the first LDD is different from a depth position of the second LDD.

9. The integrated circuit of claim 8, further comprising:

a third Lightly Doped Drain for the third device type, a depth position of the third LDD is same to the depth position of the second LDD.

10. The integrated circuit of claim 1, wherein a thickness of the second gate insulator is same to a thickness of the third gate insulator.

11. The integrated circuit of claim 1, wherein the first device type is a Deeply Depleted Channel (DDC) logic device, the second device type is a DDC analog device, the third device type is a legacy analog device.

12. The integrated circuit of claim 1, further comprising a dopant migration resistant layer between the first screening layer and the first substantially undoped layer.

13. The integrated circuit of claim 12, wherein the dopant migration resistant layer includes carbon.

14. The integrated circuit of claim 12, wherein the dopant migration resistant layer further includes SiGe deposited before forming the substantially undoped layer.