Low temperature fabrication of lateral thin film varistor

• US 9,865,674 B2
• Filed: 12/21/2016
• Issued: 01/09/2018
• Est. Priority Date: 02/26/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Graf, Richard S., Mandal, Sudeep
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/386,256
• Publication Number:
  US 20170104054A1
• Time in Patent Office: 384 Days
• Field of Search: None
• CPC Class Codes: H01C 17/006 adapted for manufacturing resistor chips
• CPC Class Codes: H01C 17/06553 composed of a combination of metals and oxides
• CPC Class Codes: H01C 17/12 by sputtering
• CPC Class Codes: H01C 17/245 by mechanical means, e.g. sand blasting, cutting, ultrasonic treatment
• CPC Class Codes: H01C 17/288 by thin film techniques
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01C 7/1013 Thin film varistors
• CPC Class Codes: H01C 7/108 Metal oxide
• CPC Class Codes: H01C 7/112 ZnO type
• CPC Class Codes: H01C 7/12 Overvoltage protection resistors series resistors structurally associated with spark gaps H01T1/16
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 28/24 : with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Claims

1. A method of forming a lateral thin film varistor comprising:

forming a continuous layer comprising alternating regions of a first metal oxide layer and a second metal oxide layer between two laterally spaced electrodes using sputtering process followed by an annealing process, including

forming the first metal oxide layer comprised of a plurality of spaced apart sections of the first metal oxide on a dielectric layer,

forming a pair of isolation layer sections, comprised of an insulating material, on the dielectric layer, laterally outside the first metal oxide layer, and

forming the second metal oxide layer comprised of a plurality of spaced apart sections of the second metal oxide on the dielectric layer, between the pair of isolation layer sections, each of the sections of the second metal oxide layer being located between a pair of the sections of the first metal oxide layer.

2. The method of claim 1, wherein the first metal oxide layer comprises zinc oxide.

3. The method of claim 1, further comprising doping the first metal oxide layer with aluminum oxide.

4. The method of claim 1, wherein the second metal oxide layer comprises bismuth oxide.

5. The method of claim 1, further comprising doping the second metal oxide layer with aluminum oxide.

6. The method of claim 1, wherein the annealing process is carried out in an inert gas atmosphere.

7. The method of claim 1, wherein the annealing process comprises heating the continuous layer to a temperature not exceeding a maximum temperature reached during the sputtering process.

8. A method of forming a lateral thin film varistor comprising:

forming a first metal oxide layer on a dielectric layer;

removing portion of the first metal oxide layer to separate the first metal oxide layer into a plurality of spaced apart sections of the first metal oxide layer on the dielectric layer;

forming a pair of isolation layer sections, comprised of an insulating material, on the dielectric layer, laterally outside the first metal oxide layer;

forming a plurality of spaced apart sections of a second metal oxide layers on the dielectric layer, between the pair of isolation layer sections, wherein each of the sections of the second metal oxide layer is located between a pair of the sections of the first metal oxide layer, and the first metal oxide layer and the second metal oxide layer form a continuous layer of alternating sections of the first and second metal oxide layers;

removing portion of the isolation layer sections adjacent to the continuous alternating layer to form openings exposing an upper surface of the dielectric layer; and

forming electrodes in the opening, the electrodes being adjacent to and contacting the continuous alternating layer.

9. The method of claim 8, wherein the forming of the first metal oxide layer on the dielectric layer comprises depositing zinc oxide using a sputtering process.

10. The method of claim 8, wherein the forming of the second metal oxide layer in the opening comprises depositing bismuth oxide using a sputtering process.

11. The method of claim 8, further comprising doping the first metal oxide layer with aluminum oxide.

12. The method of claim 8, further comprising doping the second metal oxide layer with aluminum oxide.

13. The method of claim 8, further comprising performing an annealing process.

14. The method of claim 13, wherein the annealing process comprises heating the first metal oxide layer and the second metal oxide layer to a temperature not exceeding approximately 350°

C.

15. The method of claim 13, wherein the annealing process comprises heating the second metal oxide layer to a temperature not exceeding approximately 350°

C.

16. The method of claim 13, wherein the annealing process comprises heating the first metal oxide layer and the second metal oxide layer to a temperature not exceeding a maximum temperature reached during the sputtering process.

17. The method of claim 8, further comprising:

forming a wiring level on the continuous layer of alternating sections of the first and second metal oxide layers, the electrodes, and the isolation layer;

forming conductive features in the wiring level, the conductive features being in electrical contact with the electrodes.