High voltage field balance metal oxide field effect transistor (FBM)

• US 9,865,678 B2
• Filed: 08/12/2016
• Issued: 01/09/2018
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Yilmaz, Hamza, Bobde, Madhur, Guan, Lingpeng, Hu, Jun, Kim, Jongoh, Ding, Yongping
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US15/236,263
• Publication Number:
  US 20160351659A1
• Time in Patent Office: 515 Days
• Field of Search: 257331, 257491
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a semiconductor substrate and epitaxial layer of a first conductivity type with the epitaxial layer on a top surface of the substrate. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the epitaxial layer. A first conductivity type source region is inside the body region and a drain is at a bottom surface of the substrate. An inslated gate overlaps the source and body regions. First and second trenches in the epitaxial layer are lined with insulation material and filled with electrically conductive material. Second conductivity type buried regions are positioned below the trenches. Second conductivity type charge linking paths along one or more walls of the first trench electrically connect a first buried region to the body region. A second buried region is separated from the body region by portions of the expitaxial layer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate;

a body region of a second conductivity type that is opposite of the first conductivity type disposed near a top surface of the epitaxial layer;

a source region of the first conductivity type disposed near the top surface of the epitaxial layer inside the body region;

a drain disposed at a bottom surface of the semiconductor substrate;

a gate overlapping a portion of the source region and a portion of the body region having a gate insulation layer separating the gate from the source region and the body region;

first and second trenches formed in the epitaxial layer on opposite sides of the gate, wherein the first and second trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material;

a first buried doped region of the second conductivity type positioned below the first trench;

one or more charge linking paths of the second conductivity type positioned along one or more trench walls of the first trench and configured to electrically connect the first buried doped region to the body region; and

a second buried doped region of the second conductivity type positioned below the second trench, wherein portions of the expitaxial layer separate the second buried doped region from the body region.

2. The device of claim 1, wherein the electrically conductive trench filling material in the first trench is configured to be in electrical contact with a source electrode on top of the epitaxial layer and in electrical contact with the source region.

3. The device of claim 1, wherein the electrically conductive trench filling material in the second trench is configured to be in electrical contact with the gate.

4. The device of claim 1, wherein the one or more charge linking paths are formed by diffusion.

5. The device of claim 1, wherein the gate is formed on the top surface of the epitaxial layer.

6. The device of claim 1, wherein the second buried doped region is electrically connected to the body region.

7. The device of claim 1, wherein the first and second buried doped regions are lighter doped than the body region.

8. The device of claim 1, wherein the epitaxial layer includes a surface shielded region positioned above a voltage blocking region, wherein the surface shielded region is more heavily doped than the voltage blocking region.

9. The device of claim 1, wherein the first and second buried doped regions extend to a depth substantially the same as a bottom surface of the surface shielded region.