Method of manufacturing a semiconductor device with trench gate by using a screen oxide layer

• US 9,865,726 B2
• Filed: 10/13/2016
• Issued: 01/09/2018
• Est. Priority Date: 10/14/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Laforet, David, Ouvrard, Cedric
• Primary Examiner(s): Ahmed, Shahed
• Application Number:
  US15/292,758
• Publication Number:
  US 20170110573A1
• Time in Patent Office: 453 Days
• Field of Search: 257330, 257335, 257520, 438133, 438270, 438361, 438429
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A screen oxide layer is formed on a main surface of a semiconductor layer and a passivation layer is formed on the screen oxide layer. A gate trench is formed in a portion of the semiconductor layer exposed by a mask opening in a trench mask that comprises the passivation layer. A gate dielectric is formed at least along sidewalls of the gate trench. After removing the passivation layer, dopants are implanted through the screen oxide layer to form at least one of a source zone and a body zone in the semiconductor layer.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a screen oxide layer on a main surface of a semiconductor layer and a passivation layer on the screen oxide layer;

forming a gate trench in a portion of the semiconductor layer exposed by a mask opening in a trench mask comprising the passivation layer after forming the screen oxide layer;

forming a gate dielectric at least along sidewalls of the gate trench;

implanting, after removing the passivation layer, dopants through the screen oxide layer to form at least one of a source zone and a body zone in the semiconductor layer,

forming, prior to forming the screen oxide layer, field plate structures extending from the main surface into the semiconductor layer, the field plate structures comprising an electrically conductive field electrode and a field dielectric that electrically insulates the field electrode from the semiconductor layer; and

electrically connecting the field electrode to the source zone.

2. The method of claim 1, wherein forming the gate dielectric comprises a heating treatment in an oxygen containing atmosphere.

3. The method of claim 1, wherein the gate dielectric is at least twice as thick as the screen oxide layer.

4. The method of claim 1, wherein the screen oxide layer is formed by a heating treatment in an oxygen containing atmosphere.

5. The method of claim 1, wherein the passivation layer includes a protection layer comprising a material suitable to suppress oxidation of the screen oxide layer during thermal oxidation of exposed silicon.

6. The method of claim 5, wherein the protection layer comprises a material selected from the group consisting of silicon nitride and carbon.

7. The method of claim 1, further comprising:

forming, after forming the gate dielectric, a gate electrode in the gate trench and the mask opening,

wherein forming the gate electrode includes depositing metal-containing material.

8. The method of claim 7, further comprising:

removing, after forming the gate electrode in the gate trench and the mask opening, remnants of the passivation layer.

9. The method of claim 1, wherein the passivation layer includes a trench mask layer comprising a material with high etch selectivity against the protection layer.

10. The method of claim 9, wherein the trench mask layer comprises silicon oxide or a silicate glass.

11. The method of claim 9, further comprising:

removing, before forming a gate electrode, the trench mask layer.

12. The method of claim 1, further comprising:

forming, from the implanted dopants, at least one of the source zone and the body zone directly adjoining the gate dielectric.

13. The method of claim 1, wherein a plurality of gate electrodes is formed in a plurality of separated gate trenches.

14. The method of claim 1, wherein the gate trench forms a grid and the field plate structures are formed in meshes of the grid.