Horizontal gate all around and FinFET device isolation

• US 9,865,735 B2
• Filed: 05/11/2016
• Issued: 01/09/2018
• Est. Priority Date: 05/11/2015
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Sun, Shiyu, Yoshida, Naomi, Guarini, Theresa Kramer, Jun, Sung Won, Pena, Vanessa, Sanchez, Errol Antonio C., Colombeau, Benjamin, Chudzik, Michael, Wood, Bingxi, Kim, Nam Sung
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US15/152,273
• Publication Number:
  US 20160336405A1
• Time in Patent Office: 608 Days
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Claims

1. A device structure, comprising:

a substrate;

a channel structure formed on the substrate, the channel structure having one or more silicon material layers, one or more silicon germanium material layers comprising between about 20% and about 40% germanium, and a buried oxide layer, wherein the silicon material layers, the silicon germanium material layers, and the buried oxide layer are disposed in a stacked arrangement.

2. The device structure of claim 1, wherein the buried oxide layer is disposed between the silicon germanium material layers in the stacked arrangement.

3. The device structure of claim 2, further comprising:

a liner formed on sidewalls of the channel structure, wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

4. A device structure, comprising:

a channel structure having one or more silicon material layers, one or more silicon germanium material layers comprising between about 20% and about 40% germanium, and a buried oxide layer, wherein the silicon material layers, the silicon germanium material layers, and the buried oxide layer are disposed in a stacked arrangement.

5. The device structure of claim 4, wherein the buried oxide layer is disposed between the silicon germanium material layers in the stacked arrangement.

6. The device structure of claim 5, further comprising:

a liner formed on sidewalls of the channel structure, wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

7. The device structure of claim 4, further comprising:

a liner formed on sidewalls of the channel structure.

8. The device structure of claim 7, wherein the liner is an oxynitride material, a silicon nitride materials, or combinations thereof.

9. A device structure, comprising:

a substrate;

a channel structure formed on the substrate, the channel structure having one or more silicon material layers, one or more silicon germanium material layers comprising between about 20% and about 40% germanium, and a buried oxide layer, wherein the silicon material layers, the silicon germanium material layers, and the buried oxide layer are disposed in a stacked arrangement;

source/drain regions formed on the substrate; and

a metal gate structure formed over the channel structure.

10. The device structure of claim 9, wherein the buried oxide layer is disposed between the silicon germanium material layers in the stacked arrangement.

11. The device structure of claim 9, further comprising:

a liner formed on sidewalls of the channel structure, wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

12. A device structure, comprising:

a substrate;

a channel structure having a buried oxide layer disposed on and in contact with the substrate and a silicon layer or silicon germanium layer comprising between about 20% and about 40% germanium disposed on the buried oxide layer;

source/drain regions formed on the substrate; and

a metal gate structure formed over the silicon layer or silicon germanium layer.

13. The device structure of claim 12, wherein the source/drain regions are formed from a material selected from the group consisting of silicon, phosphorous doped silicon, silicon germanium, germanium, and combinations thereof.

14. The device structure of claim 12, wherein the metal gate structure is formed from a materials selected from the group consisting of hafnium dioxide, zirconium dioxide, titanium dioxide, titanium nitride, titanium aluminide, nitride materials, and combinations thereof.