Electrode structure for resistive memory device

• US 9,865,798 B2
• Filed: 02/24/2015
• Issued: 01/09/2018
• Est. Priority Date: 02/24/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lu, Yu, Bao, Junjing, Li, Xia, Kang, Seung Hyuk
• Primary Examiner(s): Ahmad, Khaja
• Application Number:
  US14/630,438
• Publication Number:
  US 20160248002A1
• Time in Patent Office: 1,050 Days
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A semiconductor device includes an interconnect layer and a bottom electrode of a resistive memory device. The bottom electrode is coupled to the interconnect layer, and the bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

Claims

1. A semiconductor device comprising:

a conductive barrier layer;

an interconnect;

a capping layer of dielectric material between the interconnect and the conductive barrier layer, at least a portion of the capping layer in contact with the interconnect; and

an electrode of a resistive memory device, the electrode interposed between the interconnect and the conductive barrier layer, the electrode comprised of cobalt tungsten phosphorus (CoWP), wherein the conductive barrier layer has a first portion overlapping a top surface of the electrode and the capping layer and a second portion overlapping a side surface of the capping layer, wherein the second portion is perpendicular to the first portion and a height of the second portion is greater than a height of the electrode in a direction perpendicular to the top surface.

2. The semiconductor device of claim 1, wherein the electrode is deposited on the interconnect using electroless deposition.

3. The semiconductor device of claim 1, wherein the interconnect and the electrode are manufactured according to a sub-40 nanometer (nm) process.

4. The semiconductor device of claim 3, wherein a thickness of the electrode is between approximately 10 nm and 30 nm.

5. The semiconductor device of claim 1, wherein the interconnect is included in a metal layer of the semiconductor device.

6. The semiconductor device of claim 1, wherein the resistive memory device comprises a magnetic tunnel junction (MTJ) element.

7. The semiconductor device of claim 1, wherein the interconnect is disposed between first and second dielectric segments, and wherein the first and second dielectric segments and the interconnect are included in a lower portion of the semiconductor device.

8. The semiconductor device of claim 7, further comprising an oxide layer on the capping layer.

9. The semiconductor device of claim 8, wherein a combined thickness of the capping layer and the oxide layer is approximately equal to a thickness of the electrode.

10. The semiconductor device of claim 8, wherein the capping layer is comprised of silicon nitricarbide (SiCN), and wherein the oxide layer is comprised of silicon dioxide (SiO₂).

11. The semiconductor device of claim 8, further comprising an alignment mark that is etched through the capping layer and the oxide layer.

12. The semiconductor device of claim 1, wherein the electrode has a substantially uniform width.

13. The semiconductor device of claim 1, wherein the conductive barrier layer comprises a planarized conductive barrier layer.

14. The semiconductor device of claim 1, wherein the conductive barrier layer comprises tantalum nitride (TaN).

15. The semiconductor device of claim 1, wherein the electrode is positioned on the interconnect and extends from the interconnect through an opening in the capping layer to the conductive barrier layer, and wherein the electrode contacts sidewalls of the opening in the capping layer.

16. The semiconductor device of claim 1, wherein the conductive barrier layer is positioned on the electrode.

17. The semiconductor device of claim 8, wherein the conductive barrier layer is positioned on the oxide layer.

18. The semiconductor device of claim 1, further comprising an oxide layer between the capping layer and the conductive barrier layer.

19. The semiconductor device of claim 1, further comprising at least one layer between a substrate and the interconnect.

20. The semiconductor device of claim 1, wherein the resistive memory device includes a magnetic tunnel junction (MTJ), and wherein a thickness of the electrode is between approximately 10 nm and 30 nm.

21. The semiconductor device of claim 1, further comprising an oxide layer on the capping layer, the oxide layer extending over first and second dielectric segments.

22. The semiconductor device of claim 1, wherein a combined thickness of the capping layer and an oxide layer on the capping layer is approximately equal to a thickness of the electrode.

23. The semiconductor device of claim 1, wherein the capping layer and an oxide layer on the capping layer comprise silicon nitricarbide (SiCN) and silicon dioxide (SiO₂), respectively.

24. The semiconductor device of claim 1, further comprising an alignment mark that is etched through the capping layer and through an oxide layer on the capping layer.

25. The semiconductor device of claim 1, manufactured according to a sub-14 nanometer (nm) process.

26. The semiconductor device of claim 1, wherein the electrode is deposited on the interconnect using an electroless deposition technique and an acid that comprises cobalt ions, tungsten ions, and phosphorus ions.

27. A semiconductor device comprising:

a capping layer of dielectric material adjacent an interconnect and interposed between the interconnect and a conductive barrier layer; and

an electrode adjacent the interconnect and interposed between the interconnect and the conductive barrier layer, the electrode comprising cobalt tungsten phosphorus (CoWP) and included in a resistive memory device, wherein the conductive barrier layer has a first portion overlapping a top surface of the electrode and the capping layer and a second portion overlapping a side surface of the capping layer, wherein the second portion is perpendicular to the first portion and a height of the second portion is greater than a height of the electrode in a direction perpendicular to the top surface.

28. The semiconductor device of claim 27, wherein the electrode has a substantially uniform width, and wherein the resistive memory device comprises a magnetic tunnel junction (MTJ).

29. The semiconductor device of claim 27, wherein the electrode extends from the interconnect through an opening in the capping layer to the conductive barrier layer.

30. The semiconductor device of claim 27, wherein the conductive barrier layer comprises a tantalum nitride (TaN) layer adjacent an oxide layer.