Electronic device and method for fabricating the same

• US 9,865,806 B2
• Filed: 11/17/2016
• Issued: 01/09/2018
• Est. Priority Date: 06/05/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Choi, Won-Joon, Park, Ki-Seon, Dong, Cha-Deok, Lee, Bo-Mi, Kim, Guk-Cheon, Noh, Seung-Mo, Lee, Min-Suk, Park, Chan-Sik, Kim, Jae-Heon, Kim, Choi-Dong, Kim, Jae-Hong, Kim, Yang-Kon, Lim, Jong-Koo, Kim, Jeong-Myeong
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US15/354,365
• Publication Number:
  US 20170069837A1
• Time in Patent Office: 418 Days
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Claims

1. An electronic device comprising semiconductor memory, wherein the semiconductor memory includes:

a substrate;

an under layer disposed over the substrate and including conductive hafnium silicate;

a free layer disposed over the under layer and having a variable magnetization direction;

a tunnel barrier layer disposed over the free layer; and

a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and

wherein the free layer includes;

a first ferromagnetic material;

a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and

an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

2. The electronic device of claim 1, wherein the conductive hafnium silicate is amorphous.

3. The electronic device of claim 1, wherein the semiconductor memory further comprising:

an interlayer dielectric layer disposed over the substrate, and having a recess which exposes a portion of the substrate; and

a bottom contact filled in a lower portion of the recess, and

wherein the under layer is disposed over the bottom contact and fills a remaining portion of the recess, and the free layer is disposed over the interlayer dielectric layer.

4. The electronic device of claim 1, wherein a width of a top surface of the under layer is greater than a width of a bottom surface of the free layer.

5. The electronic device of claim 1, wherein the recess has a wine glass-like shape.

6. An electronic device comprising semiconductor memory, wherein the semiconductor memory includes:

a substrate;

an interlayer dielectric layer disposed over the substrate, and having a recess which exposes a portion of the substrate;

a bottom contact filled in a lower portion of the recess;

an under layer disposed over the bottom contact and fills a remaining portion of the recess;

a free layer disposed over the under layer and having a variable magnetization direction;

a tunnel barrier layer disposed over the free layer; and

a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and

wherein the free layer includes;

a first ferromagnetic material;

a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and

an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

7. The electronic device of claim 6, wherein the recess has a wine glass-like shape.

8. The electronic device of claim 6, wherein the under layer includes a first metal which has a higher electron affinity than a component included in the free layer and the pinned layer, and an oxide of the first metal is an insulating material.

9. The electronic device of claim 8, wherein the semiconductor memory further comprising:

a spacer formed over sidewalls of the free layer, the tunnel barrier layer and the pinned layer and including the oxide of the first metal.

10. The electronic device of claim 8, wherein the first metal includes at least one of Al, Hf, Ti or Mg.

11. The electronic device of claim 8, wherein the under layer includes multiple layers, an uppermost layer of the multiple layers includes the first metal.

12. The electronic device of claim 8, wherein the under layer includes a first under layer formed along a sidewall and a bottom surface of the remaining portion of the recess, and a second under layer disposed over the first under layer and surrounded by the first under layer except for a top surface of the second under layer, and

the first under layer includes the first metal.

13. The electronic device of claim 12, the first metal includes at least one of Al, Hf, Ti or Mg, and

the second under layer includes Ta.

14. The electronic device of claim 12, wherein the free layer covers the second under layer and exposes at least a part of the first under layer.

15. The electronic device of claim 6, wherein the under layer includes first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers.

16. The electronic device of claim 15, wherein the barrier layer includes a first material having an FCC (Face Centered Cubic) structure and a second material having a wurtzite structure.

17. The electronic device of claim 16, wherein the barrier layer includes an alloy of the first and second materials.

18. The electronic device of claim 17, wherein the first material comprises HfN, TiN, MoN, ZrN, or MgO, and the second material comprises AlN, AgI, ZnO, CdS, CdSe, a-SiC, GaN, or BN.

19. The electronic device of claim 15, wherein the first metal layer has an HCP (Hexagonal Closed Packed) structure or a crystal structure of NaCl, and the second metal layer comprises a metal nitride layer including a light metal.

20. The electronic device of claim 15, wherein the first metal layer includes Hf, Zr, Mg, Ru, or Os, ZrN, HfN, or TiN, and the second metal layer comprises Al or Ti.