Multilevel buck converter with a flying capacitor and charge pump

• US 9,866,113 B1
• Filed: 12/15/2016
• Issued: 01/09/2018
• Est. Priority Date: 12/15/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Assaad, Rida Shawky, Evans, David Wayne
• Primary Examiner(s): Behm, Harry
• Assistant Examiner(s): Novak, Peter
• Application Number:
  US15/379,746
• Time in Patent Office: 390 Days
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/078 with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

Methods and apparatus for flying capacitor balancing in multilevel converters are disclosed. Example flying capacitor balancing circuitry can include voltage difference sense and control circuitry and duty cycle timing adjustment circuitry. The voltage difference sense and control circuitry can generate a compensation control signal for the duty cycle timing adjustment circuitry.

Claims

1. An apparatus to be coupled with a flying capacitor through flying capacitor couplers comprising:

a multilevel DC-DC converter having an operating mode having a duty cycle and including a series connection of at least four primary switches extending between a DC voltage rail and a ground reference, the at least four primary switches including a central high-side primary switch coupled in series between a first high-side primary switch and a central low-side primary switch, the central low-side primary switch coupled in series between the central high-side primary switch and a ground referenced low-side primary switch;

flying capacitor couplers including a first coupling node to a series connection of the first high-side primary switch and the central high-side primary switch, the flying capacitor couplers further including a second coupling node to a series connection of the central low-side primary switch and the ground referenced low-side primary switch; and

voltage difference sense and control circuitry coupled with the DC voltage rail and the first coupling node of the flying capacitor to sense when there is a difference between a voltage of flying capacitor and half of the DC voltage rail, and to generate a compensation control signal in response to the difference between the voltage of flying capacitor and half of the DC voltage rail.

2. The apparatus as in claim 1 including duty cycle timing adjustment circuitry coupled with the voltage difference sense and control circuitry to generate a duty cycle adjustment signal in response to the compensation control signal generated by the voltage difference sense and control circuitry.

3. The apparatus as in claim 2 including duty cycle control circuitry coupled between the duty cycle timing adjustment circuitry and control gate inputs of the four primary switches of the multilevel DC-DC converter to adjust duty cycle of the operating mode of the multilevel DC-DC converter in response to the duty cycle adjustment signal, and to balance the voltage of the flying capacitor to be half of the DC voltage rail.

4. The apparatus as in claim 1 in which the voltage difference sense and control circuitry includes peak current mode control loop circuitry operating to control balance of the voltage of the flying capacitor at half of the DC voltage rail.

5. The apparatus as in claim 4 in which the voltage difference sense and control circuitry includes voltage mode control loop circuitry operating to further control balance of the voltage of the flying capacitor at half of the DC voltage rail.

6. The apparatus as in claim 4 in which the peak current mode control loop circuitry includes a first peak current ramp generator generating a first peak current ramp output and further includes a second peak current ramp generator generating a second peak current ramp output, the first and second peak current ramp generators being in antiphase with one another.

7. The apparatus as in claim 5 in which:

the multilevel DC-DC converter includes an output node coupled between the central high-side primary switch and the central low-side primary switch; and

the peak current mode control loop circuitry includes an input coupled with the output node of the multilevel DC-DC converter to sense a peak current at the output node of the multilevel DC-DC converter when the multilevel DC-DC converter is operating in the operating mode of the multilevel DC-DC converter.

8. The apparatus as in claim 5 in which:

the multilevel DC-DC converter includes an output node coupled between the central high-side primary switch and the central low-side primary switch; and

the voltage mode control loop circuitry includes an input coupled with the output node of the multilevel DC-DC converter to sense a voltage at the output node of the multilevel DC-DC converter when the multilevel DC-DC converter is operating in the operating mode of the multilevel DC-DC converter.

9. The apparatus as in claim 8 in which:

the voltage mode control loop circuitry includes voltage divider circuitry to divide the voltage sensed at the output node of the multilevel DC-DC converter into a divided voltage; and

the voltage mode control loop circuitry includes a first differential amplifier to compare a voltage reference to the divided voltage and to generate an output difference voltage signal.

10. The apparatus as in claim 9 in which:

the peak current mode control loop circuitry includes an input coupled with the output node of the multilevel DC-DC converter to sense a peak current at the output node of the multilevel DC-DC converter when the multilevel DC-DC converter is operating in the operating mode of the multilevel DC-DC converter;

the peak current mode control loop circuitry includes a first peak current ramp generator generating a first peak current ramp output in response to the peak current sensed at the output node of the multilevel DC-DC converter; and

the peak current mode control loop circuitry includes a second differential amplifier to compare the first peak current ramp output of the first peak current ramp generator to the output difference voltage signal of the voltage mode control loop circuitry and to generate a first peak current difference signal.

11. The apparatus as in claim 10 in which:

the peak current mode control loop circuitry includes a second peak current ramp generator generating a second peak current ramp output in response to the peak current sensed at the output node of the multilevel DC-DC converter; and

the peak current mode control loop circuitry includes a third differential amplifier to compare the second peak current ramp output of the second peak current ramp generator to the output difference voltage signal of the voltage mode control loop circuitry and to generate a second peak current difference signal.

12. The apparatus as in claim 1 in which the voltage difference sense and control circuitry includes delay compensation circuitry, the delay compensation circuitry including a differential transconductance amplifier and logic gates for generating the compensation control signal in response to the difference between the voltage of the flying capacitor and half of the DC voltage rail.

13. The apparatus as in claim 11 in which the voltage difference sense and control circuitry includes delay compensation circuitry including:

a differential transconductance amplifier including differential inputs coupled with the voltage of the flying capacitor and half of the DC voltage rail, and the differential transconductance amplifier including differential outputs; and

first and second logic gates having respective first inputs coupled with the first and second peak current ramp outputs, having respective second inputs coupled with the differential outputs of the differential transconductance amplifier, and having respective outputs of the compensation control signal.

14. The apparatus as in claim 1 in which the multilevel DC-DC converter is a three level DC-DC converter.

15. A method of operating a multilevel DC-DC converter in an operating mode having a duty cycle, the method comprising:

driving respective control gates of at least four series connected primary switches of the multilevel DC-DC converter in the duty cycle of the operating mode; and

sensing when there is a difference between a voltage of a flying capacitor and half of a DC voltage rail of the multilevel DC-DC converter; and

generating a compensation control signal in response to the difference between the voltage of flying capacitor and half of the DC voltage rail.

16. The method as in claim 15 including generating a duty cycle adjustment signal in response to the compensation control signal.

17. The method as in claim 16 including adjusting the duty cycle of the operating mode of the multilevel DC-DC converter in response to the duty cycle adjustment signal.

18. The method as in claim 17 including balancing the voltage of the flying capacitor to be half of the DC voltage rail of the multilevel DC-DC converter.

19. An apparatus comprising:

a multilevel DC-DC converter having an operating mode having a duty cycle and including a series connection of at least four primary switches extending between a DC voltage rail and a ground reference, the at least four primary switches including a central high-side primary switch coupled in series between a first high-side primary switch and a central low-side primary switch, the central low-side primary switch coupled in series between the central high-side primary switch and a ground referenced low-side primary switch;

a flying capacitor including a first coupling node to a series connection of the first high-side primary switch and the central high-side primary switch, the flying capacitor further including a second coupling node to a series connection of the central low-side primary switch and the ground referenced low-side primary switch; and

voltage difference sense and control circuitry coupled with the DC voltage rail and the first coupling node of the flying capacitor to sense when there is a difference between a voltage of flying capacitor and half of the DC voltage rail, and to generate a compensation control signal in response to the difference between the voltage of flying capacitor and half of the DC voltage rail.

20. The apparatus as in claim 19 including:

duty cycle timing adjustment circuitry coupled with the voltage difference sense and control circuitry to generate a duty cycle adjustment signal in response to the compensation control signal generated by the voltage difference sense and control circuitry; and

duty cycle control circuitry coupled between the duty cycle timing adjustment circuitry and control gate inputs of the four primary switches of the multilevel DC-DC converter to adjust duty cycle of the operating mode of the multilevel DC-DC converter in response to the duty cycle adjustment signal, and to balance the voltage of the flying capacitor to be half of the DC voltage rail.