Tuning capacitance to enhance FET stack voltage withstand

• US 9,866,212 B2
• Filed: 03/04/2016
• Issued: 01/09/2018
• Est. Priority Date: 04/26/2007
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Englekirk, Robert Mark
• Primary Examiner(s): Patel, Reema
• Application Number:
  US15/061,909
• Publication Number:
  US 20170026035A1
• Time in Patent Office: 676 Days
• Field of Search: None
• CPC Class Codes: H01H 11/00 Apparatus or processes specially adapted for the manufacture of electric switches processes specially adapted for manufacture of rectilinearly movable switches having a plurality of operating members associated with different sets of contacts, e.g. keyboards, H01H13/88
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: Y10T 29/49105 Switch making

Abstract

An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Claims

1. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds;

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds;

forming a top endnode at a top of said stack of series coupled transistors;

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors; and

coupling at least one compensation capacitor across said top endnode and at least one of said plurality of internal nodes to voltage balance said stack of series coupled transistors.

2. The method of claim 1 further comprising coupling said at least one compensation capacitor to ground.

3. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds;

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds;

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors; and

coupling at least one compensation capacitor across at least two of said plurality of internal nodes to voltage balance said stack of series coupled transistors.

4. The method of claim 3 further comprising coupling said at least one compensation capacitor to ground.

5. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds;

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds;

forming a bottom endnode at a bottom of said stack of series coupled transistors;

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors; and

coupling at least one compensation capacitor across at least one of said plurality of internal nodes and said bottom endnode to voltage balance said stack of series coupled transistors.

6. The method of claim 5 further comprising coupling said at least one compensation capacitor to ground.

7. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds;

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds;

forming a top endnode at a top of said stack of series coupled transistors;

forming a bottom endnode at a bottom of said stack of series coupled transistors; and

coupling at least one compensation capacitor across said top endnode and said bottom endnode to voltage balance said stack of series coupled transistors.

8. The method of claim 7 further comprising coupling said at least one compensation capacitor to ground.

9. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds;

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds;

forming a top endnode at a top of said stack of series coupled transistors;

forming a bottom endnode at a bottom of said stack of series coupled transistors;

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors; and

coupling at least one compensation capacitor across at least one of;

i) said top endnode and at least one of said plurality of internal nodes, ii) at least two of said plurality of internal nodes, iii) at least one of said plurality of internal nodes and said bottom endnode, and iv) said top endnode and said bottom endnode, to voltage balance said stack of series coupled transistors.

10. The method of claim 9 further comprising coupling said at least one compensation capacitor to ground.

11. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds;

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds;

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors; and

coupling at least one compensation capacitor across at least one of said plurality of internal nodes and ground to voltage balance said stack of series coupled transistors.

12. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds; and

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds.

13. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming said series coupled stacked transistors, wherein at least one of said series coupled stacked transistors has a lower intrinsic Cds and wherein at least another of said series of coupled stacked transistors has a higher intrinsic Cds; and

establishing a difference between said higher intrinsic Cds and said lower intrinsic Cds of a predetermined amount.

14. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming said series coupled stacked transistors, wherein at least one of said series coupled stacked transistors has a lower intrinsic Cds and wherein at least another of said series of coupled stacked transistors has a higher intrinsic Cds;

establishing a difference between said higher intrinsic Cds and said lower intrinsic Cds of a predetermined amount;

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors;

forming a plurality of gate insulation compensation capacitors; and

coupling at least one gate insulation compensation capacitor across at least two of said plurality of internal nodes to voltage balance said stack of series coupled transistors.

15. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors;

coupling at least one compensation capacitor across at least one of said plurality of internal nodes and ground to voltage balance said stack of series coupled transistors;

forming a plurality of gate resistive impedances of said stack of series coupled transistors; and

forming a plurality of gate capacitive impedances of said stack of series coupled transistors, wherein at least one of said plurality of gate resistive impedances and at least one of said plurality of gate capacitive impedances combine to form a low pass filter.

16. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming at least one of said series coupled stacked transistors having an intrinsic drain-source capacitance Cds;

forming internal nodes between adjacent transistors of said stack of series coupled transistors, at least one of said internal nodes having an internal node capacitance Cpd; and

establishing a ratio of said internal node capacitance Cpd to said intrinsic drain-source capacitance Cds of less than a predetermined value.

17. The method of claim 16 further comprising coupling said internal node capacitance Cpd to ground.

18. The method of claim 16 further comprising coupling at least one compensation capacitor across at least two of said plurality of internal nodes to voltage balance said stack of series coupled transistors.

19. The method of claim 18 further comprising coupling said at least one compensation capacitor to ground.

20. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming said series coupled stacked transistors, wherein at least one of said series coupled stacked transistors has a lower intrinsic Cds and wherein at least another of said series of coupled stacked transistors has a higher intrinsic Cds;

establishing a difference between said higher intrinsic Cds and said lower intrinsic Cds of a predetermined amount;

forming at least one internal node between a pair of adjacent transistors of said stack of series coupled transistors, said at least one internal node having an internal node capacitance Cpd; and

establishing a ratio of said internal node capacitance Cpd to said lower intrinsic Cds of less than a predetermined value.

21. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

coupling one or more capacitive features to nodes of the stack, the one or more capacitive features including parasitic capacitances.

22. A method of fabricating a stacked RF switch that includes a multiplicity plurality of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, the method comprising

establishing total effective drain-source capacitance Cds values not encompassing parasitic capacitances Cpd that are significantly different for different transistors for each constituent transistor in the stack, wherein and at least two transistors are configured such that their intrinsic Cds values differ from each other by at least 0.5%.

23. A method of balancing voltage distribution across a stack of series coupled transistors, the method comprising:

forming a first of said series coupled stacked transistors of a first intrinsic drain-source capacitance Cds;

forming a second of said series coupled stacked transistors of a second intrinsic Cds, wherein said second intrinsic Cds differs by at least a predetermined amount to said first intrinsic Cds;

forming a top endnode at a top of said stack of series coupled transistors;

forming a plurality of internal nodes between pairs of adjacent transistors of said stack of series coupled transistors; and

coupling one or more compensation capacitors across intrinsic Cds'"'"'s of the stacked transistors,

to voltage balance said stack of series coupled transistors.