System and method for high-performance, low-power data center interconnect fabric

• US 9,866,477 B2
• Filed: 09/01/2016
• Issued: 01/09/2018
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: III Holdings 2, LLC
• Original Assignee: III Holdings 2, LLC
• Inventors: Davis, Mark Bradley, Borland, David James
• Primary Examiner(s): Khirodhar, Maharishi
• Assistant Examiner(s): Hunt, Kenneth P
• Application Number:
  US15/254,111
• Publication Number:
  US 20160373354A1
• Time in Patent Office: 495 Days
• Field of Search: 370351-430, 709238-244, 711108
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 45/74 Address processing for routing
• CPC Class Codes: H04L 45/74591 using content-addressable memories [CAM]
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/253 using establishment or release of connections between ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/351 : for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/356 : for storage area networks
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02B 70/30 : Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 : Reducing energy consumption in communication networks

Abstract

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Claims

1. A switch system comprising:

a plurality of nodes, wherein each node of the plurality of nodes includes a switch;

a plurality of links associated with each node, wherein the plurality of links are configured to connect nodes in the plurality of nodes to create a topology of a switch fabric for routing data through the plurality of nodes;

a management processor in at least one of the nodes, wherein the management processor is configured to control the routing of data through the switch fabric; and

at least one routing header processor at each switch, wherein the at least one routing header processor is configured to access a content addressable memory with a tag to determine if an incoming broadcast packet has crossed through a particular switch.

2. The switch system of claim 1, wherein the tag comprises a broadcast identifier.

3. The switch system of claim 1, wherein the at least one routing header processor is further configured to standardize one or more fields in the incoming broadcast packet.

4. The switch system of claim 3, wherein the one or more fields comprise a preamble field, a start of frame field, and an inter-frame gap field.

5. The switch system of claim 1, wherein the at least one routing header processor is further configured to add one or more fields to the incoming broadcast packet such that the incoming broadcast packet can be received by the fabric switch.

6. The switch system of claim 5, wherein the at least one routing header processor is further configured to strip the one or more fields from the incoming broadcast packet before the incoming broadcast packet leaves the fabric switch.

7. The switch system of claim 1, wherein the at least one routing header processor is further configured to generate a routing frame header for a frame packet using a routing table.

8. The switch system of claim 7, wherein the frame packet comprises the routing frame header and a core portion of an Ethernet frame.

9. The switch system of claim 7, wherein the at least one routing header processor is further configured to convert the frame packet to an Ethernet packet.

10. The switch system of claim 9, wherein the conversion is performed as the frame packet is entering or leaving the fabric switch.

11. A method comprising:

controlling, using a management processor in one of a plurality of nodes of a fabric switch, routing of data through the switch fabric;

generating, by at least one routing header processor in one of the plurality of nodes, a routing frame header for a frame packet using a routing table, wherein the routing frame header includes a domain identifier and a management domain state associated with a media access control (MAC) layer that generated the routing frame header; and

converting, by the at least one routing header processor, the frame packet to an Ethernet packet.

12. The method of claim 11, wherein the frame packet comprises the routing frame header and a core portion of an Ethernet frame.

13. The method of claim 11, wherein the conversion is performed as the frame packet is entering or leaving the fabric switch.

14. A method comprising:

controlling, using a management processor of a fabric switch that includes a plurality of nodes, routing of data through the switch fabric;

accessing, by at least one routing header processor in the fabric switch, a content addressable memory with a tag to determine if an incoming broadcast packet has crossed through a particular switch; and

standardizing, by the at least one routing header processor, one or more fields in the incoming broadcast packet.

15. The method of claim 14, wherein the one or more fields comprises a preamble field, a start of frame field, and an inter-frame gap field.

16. The method of claim 14, further comprising adding, by the at least one routing header processor, one or more fields to the incoming broadcast packet such that the incoming broadcast packet can be received by the fabric switch.

17. The method of claim 16, further comprising stripping, by the at least one routing header processor, the one or more fields from the incoming broadcast packet before the incoming broadcast packet leaves the fabric switch.