Device comprising programmable logic element
First Claim
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1. A device comprising:
- a first circuit; and
a second circuit comprising;
programmable logic elements;
third circuits each comprising first and second transistors and a memory circuit comprising a magnetic tunnel junction element; and
a fourth circuit comprising a third transistor, one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor,wherein the fourth circuit is configured to write configuration data to the memory circuit through the first transistor to control conduction between the programmable logic elements and change contents of logic operations in the programmable logic elements in a first period,wherein the fourth circuit is configured to write data to the memory circuit through the first transistor and read the data from the memory circuit through the second transistor in a second period,wherein the third transistor is turned on in the second period, andwherein the first period is a period of an operation test of the first circuit and the second period is a period in which the operation test of the first circuit is not performed.
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Abstract
Provided is a device capable of generating test patterns even after the design stage. The area of a circuit which is included in the device and unnecessary during normal operation can be reduced. The device includes a first circuit and a second circuit. The second circuit includes a plurality of third circuits, a plurality of fourth circuits, and a fifth circuit and has a function of generating a signal for testing operation of the first circuit and a function of operating as part of the first circuit. The fourth circuit has a function of storing a first data and a function of storing a second data. The fifth circuit has a function of writing the first data to the plurality of fourth circuits, a function of writing the second data to the plurality of fourth circuits, and a function of reading the second data from the plurality of fourth circuits.
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Citations
19 Claims
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1. A device comprising:
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a first circuit; and a second circuit comprising; programmable logic elements; third circuits each comprising first and second transistors and a memory circuit comprising a magnetic tunnel junction element; and a fourth circuit comprising a third transistor, one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, wherein the fourth circuit is configured to write configuration data to the memory circuit through the first transistor to control conduction between the programmable logic elements and change contents of logic operations in the programmable logic elements in a first period, wherein the fourth circuit is configured to write data to the memory circuit through the first transistor and read the data from the memory circuit through the second transistor in a second period, wherein the third transistor is turned on in the second period, and wherein the first period is a period of an operation test of the first circuit and the second period is a period in which the operation test of the first circuit is not performed. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device comprising:
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a first circuit; and a second circuit comprising; programmable logic elements; third circuits each comprising first and second transistors and a memory circuit comprising a magnetic tunnel junction element; and a fourth circuit comprising a third transistor, one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, wherein the second circuit is configured to store configuration data to generate a signal for a testing operation of the first circuit and configured to operate as a memory of the first circuit after the testing operation, wherein the fourth circuit is configured to write the configuration data to the memory circuit through the first transistor to control conduction between the programmable logic elements and change contents of logic operations in the programmable logic elements, wherein the fourth circuit is configured to write data to the memory circuit through the first transistor and read the data from the memory circuit through the second transistor, and wherein the third transistor is turned on after the testing operation. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A device comprising:
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a first circuit; and a second circuit comprising; programmable logic elements; third circuits each comprising first and second transistors and a memory circuit comprising a magnetic tunnel junction element; and a driver circuit comprising a third transistor, one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, wherein the second circuit is configured to store configuration data to generate a signal for a testing operation of the first circuit and configured to operate as a memory storing data of the first circuit after the testing operation, wherein the configuration data are input to and stored in the driver circuit one by one and are output from the driver circuit to the memory circuits through the first transistors simultaneously to change contents of logic operations in the programmable logic elements, wherein the data are input and stored in the driver circuit simultaneously and are output from the driver circuit to the memory circuits through the first transistors simultaneously and the data are read from the memory circuits through the second transistor, and wherein the third transistor is turned on after the testing operation. - View Dependent Claims (16, 17, 18, 19)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsKurokawa, Yoshiyuki
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Primary Examiner(s)Assouad, Patrick
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Assistant Examiner(s)Yodichkas, Khristopher
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Application NumberUS14/612,745Publication NumberTime in Patent Office1,078 DaysField of Search3247503US Class CurrentCPC Class CodesG01R 31/2884 using dedicated test connec...G01R 31/31813 Test pattern generatorsG11C 11/16 using elements in which the...G11C 2029/3602 Pattern generatorG11C 29/36 Data generation devices, e....H01L 27/0688 Integrated circuits having ...H10B 61/00 Magnetic memory devices, e....
