Interleaved all-level programming of non-volatile memory
First Claim
1. A method for programming a non-volatile memory device having a plurality of word lines each operatively coupled to a plurality of multi-level storage cells, the method comprising:
- programming word line n to an intermediate voltage level;
programming word line n+1 to an intermediate voltage level;
programming word line n to its target voltage level;
programming word line n+2 to an intermediate voltage level;
programming word line n+1 to its target voltage level;
programming word line n+2 to its target voltage level; and
suppressing reads to word line n, word line n+1, and word line n+2, until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level.
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Abstract
Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.
15 Citations
25 Claims
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1. A method for programming a non-volatile memory device having a plurality of word lines each operatively coupled to a plurality of multi-level storage cells, the method comprising:
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programming word line n to an intermediate voltage level; programming word line n+1 to an intermediate voltage level; programming word line n to its target voltage level; programming word line n+2 to an intermediate voltage level; programming word line n+1 to its target voltage level; programming word line n+2 to its target voltage level; and suppressing reads to word line n, word line n+1, and word line n+2, until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A storage controller device, comprising:
one or more memory controllers configured to facilitate movement of staged data from a staging buffer to a non-volatile memory, the non-volatile memory having a plurality of word lines each operatively coupled to a plurality of storage cells, at least one of the one or more controllers configured to program word line n to an intermediate voltage level, program word line n+1 to an intermediate voltage level, program word line n to its target voltage level, program word line n+2 to an intermediate voltage level, program word line n+1 to its target voltage level, program word line n+2 to its target voltage level, and suppress reads to word line n, word line n+1, and word line n+2 until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A solid-state storage system, comprising:
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a host interface configured to receive data for storage; a phase change memory with switch (PCMS) configured to stage data received by the host interface; a PCMS controller configured to facilitate the writing of data to the PCMS; NAND flash memory configured to store data staged in the PCMS and having a plurality of word lines each operatively coupled to a plurality of storage cells; a NAND controller configured to facilitate the writing of data to the NAND flash memory; a processor configured to facilitate movement of staged data from the PCMS to the NAND flash memory, wherein processor is configured to program word line n to an intermediate voltage level, program word line n+1 to an intermediate voltage level, program word line n to its target voltage level, program word line n+2 to an intermediate voltage level, program word line n+1 to its target voltage level, program word line n+2 to its target voltage level, and suppress reads to word line n, word line n+1, and word line n+2 until each of word line n, word line n+1, and word line n+2 is programmed to its target voltage level. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification