Memory flash apparatus and method for providing device upgrades over a standard interface

• US 9,870,220 B2
• Filed: 12/05/2008
• Issued: 01/16/2018
• Est. Priority Date: 12/05/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lerman, Mikhael
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): BARTELS, CHRISTOPHER A.
• Application Number:
  US12/329,501
• Publication Number:
  US 20100146159A1
• Time in Patent Office: 3,329 Days
• Field of Search: None
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories

Abstract

An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB (universal serial bus) port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM (programmable read only memory), and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS (basic input/output system), may be modified or replaced.

Claims

1. An electronic host device comprising:

a processor;

a memory subsystem storing a boot code, said processor operative to boot with said boot code; and

routing logic in the electronic host device, operatively coupled to said memory subsystem and at least one communication port of said electronic host device, said communication port being accessible externally from said electronic host device, said communication port providing access to an internal bus of said electronic host device,

wherein said routing logic is operative to route boot code upgrade data, from a peripheral stand-alone device that is external to said electronic host device, to said memory subsystem to bypass said processor in response to said peripheral stand-alone device transmitting a data packet to the electronic host device indicating that a boot code upgrade will be performed when connected at said at least one communication port, said boot code upgrade data for modifying or replacing said boot code stored within said memory subsystem.

2. The electronic host device of claim 1, wherein said boot code is a Basic Input/Output System (BIOS) code.

3. The electronic host device of claim 1, wherein said routing logic is further operable to receive said data packet from said peripheral stand-alone device, said data packet indicating that said peripheral stand-alone device is a PROM (programmable read only memory) programming device, and in response to receiving said data packet, obtain exclusive control of said internal bus to enable programming commands to flow from said peripheral stand-alone device to said memory subsystem, said memory subsystem including a PROM.

4. The electronic host device of claim 1, wherein said at least one communication port is a Universal Serial Bus (USB) port, wherein said internal bus includes a routing pathway from said USB port to said memory subsystem, and wherein said memory subsystem includes a flash type PROM.

5. An integrated circuit comprising the routing logic of claim 1.

6. The electronic host device of claim 1, having said peripheral stand-alone device connected at said at least one communication port, wherein said peripheral stand-alone device is operable to indicate to said routing logic that said peripheral stand-alone device is a PROM programming device.

7. The electronic host device of claim 1, wherein said peripheral stand-alone device is a USB device.

8. The electronic host device of claim 1, wherein said communication port is a USB port.

9. A host device comprising:

an interface module having a communication port for communicating with a peripheral stand-alone device attached to said communication port;

a memory interface module for communicating with a memory subsystem of the host device including a boot Programmable Read Only Memory (PROM); and

a routing logic coupled to said interface module and said memory interface module, said routing logic operative to route boot code upgrade data, from said peripheral stand-alone device that is external to said host device, to said boot PROM to bypass a processor of said host device in response to said peripheral stand-alone device transmitting a data packet to the electronic host device indicating that a boot code upgrade will be performed when connected at said communication port, said processor operative to boot from said boot PROM, said boot code upgrade data for modifying a boot code stored on said boot PROM.

10. The memory interface device of claim 9, wherein said boot code is a Basic Input/Output System (BIOS) code.

11. The memory interface device of claim 9, wherein said routing logic is further operable to receive said data packet from said peripheral stand-alone device, said data packet indicating that said peripheral stand-alone device is a PROM programming device, and in response to receiving said data packet, obtain control of an internal bus between said memory interface module and said memory subsystem, to enable programming commands to flow from said peripheral stand-alone device to said memory subsystem, said memory subsystem including said PROM.

12. The memory interface device of claim 11, wherein said communication port is a USB port, wherein said internal bus includes a routing pathway from said USB port to said memory subsystem, and wherein said PROM is a flash type PROM.

13. An integrated circuit comprising the memory interface device of claim 9.

14. A method comprising:

detecting a device at an interface port of an electronic host device;

detecting, by a routing logic, that a peripheral stand-alone device, connected at a communication port of said electronic host device, is a PROM (programmable read only memory) programming device, wherein said peripheral stand-alone device is external to said electronic host device; and

routing boot code upgrade data, from said peripheral stand-alone device to a memory subsystem of said electronic host device to bypass a processor of said electronic host device in response to said peripheral stand-alone device transmitting a data packet to the electronic host device indicating that a boot code upgrade will be performed when connected, said boot code upgrade data for modifying or replacing said boot code stored within said memory subsystem, said processor operative to boot from said boot code.

15. The method of claim 14, wherein routing boot code upgrade data from said peripheral stand-alone device, to a memory subsystem of said electronic host device, said boot code upgrade data comprises:

modifying or replacing said boot code wherein said boot code is a Basic Input/Output System (BIOS) code.

16. The method of claim 14, comprising:

receiving said data packet, by said routing logic, from said peripheral stand-alone device, said data packet indicating that said peripheral stand-alone device is a PROM programming device; and

obtaining, in response to receiving said data packet, exclusive control of an internal bus to enable programming commands to flow from said peripheral stand-alone device to said memory subsystem, said memory subsystem including a PROM.

17. The method of claim 14, wherein detecting, by a routing logic, that a peripheral stand-alone device, connected at a communication port of an electronic host device, is a PROM (programmable read only memory) programming device, further comprises:

detecting said peripheral stand-alone device at a USB port wherein said communication port is said USB port.

18. The method of claim 17, wherein routing said boot code upgrade data from said peripheral stand-alone device, to a memory subsystem of said electronic host device further comprises:

routing said boot code upgrade data, by said routing logic, from said peripheral stand-alone device via said USB port and an internal bus that includes a routing pathway from said USB port to said memory subsystem, and wherein said memory subsystem includes a flash type PROM.

19. A non-transitory computer readable memory comprising:

executable instructions for execution by at least one processor, that when executed cause said at least one processor to;

detect a device at an interface port of an electronic host device including a processor;

detect that a peripheral stand-alone device, connected at a communication port of said electronic host device including said at least one processor, is a PROM (programmable read only memory) programming device, wherein said peripheral stand-alone device is external to said electronic host device; and

route boot code upgrade data, from said peripheral stand-alone device to a memory subsystem of said electronic host device, to bypass said processor of said electronic host device in response to said peripheral stand-alone device transmitting a data packet to the electronic host device indicating that a boot code upgrade will be performed, said boot code upgrade data for modifying or replacing said boot code stored within said memory subsystem, said processor operative to boot with said boot code.

20. The computer readable memory of claim 19, wherein said executable instructions, when executed further cause the one or more processors to:

modify or replace said boot code wherein said boot code is a Basic Input/Output System (BIOS) code.

21. The computer readable memory of claim 19, wherein said executable instructions, when executed further cause the one or more processors to:

receive said data packet from said peripheral stand-alone device, said data packet indicating that said peripheral stand-alone device is a PROM programming device; and

obtain, in response to receiving said data packet, exclusive control of an internal bus to enable programming commands to flow from said peripheral stand-alone device to said memory subsystem, said memory subsystem including a PROM.

22. The computer readable memory of claim 19, wherein said executable instructions, when executed further cause the one or more processors to:

detect said peripheral stand-alone device at a USB (universal serial bus) port wherein said communication port is said USB port.

23. The computer readable memory of claim 22, wherein said executable instructions, when executed further cause the one or more processors to:

route said boot code upgrade data from said peripheral stand-alone device via said USB port and an internal bus that includes a routing pathway from said USB port to said memory subsystem, and wherein said memory subsystem includes a flash type PROM.