Multi-threaded processing with reduced context switching

• US 9,870,252 B2
• Filed: 11/13/2013
• Issued: 01/16/2018
• Est. Priority Date: 08/15/2007
• Status: Active Grant

• Current Assignee: Sony Interactive Entertainment Inc. (Sony Group Corp.)
• Original Assignee: Sony Interactive Entertainment Inc. (Sony Group Corp.)
• Inventors: Bates, John P.
• Primary Examiner(s): PUENTE, EMERSON C
• Assistant Examiner(s): Do, Steven
• Application Number:
  US14/078,867
• Publication Number:
  US 20140075450A1
• Time in Patent Office: 1,525 Days
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.

Claims

1. In a computer system having one or more processors coupled to a memory, a method for multi-threaded processing, comprising:

notifying one or more of the processors running a first thread or thread group of a pre-emption by a second thread or thread group characterized by a higher priority than the first thread;

notifying the one or more of the processors of a time limit for pre-emption associated with the second thread or thread group, wherein the time limit for pre-emption specifies how long the second thread or thread group can wait before preempting the first thread or thread group, wherein the time limit is less than a time needed for a context switch from the first thread or thread group to the second thread or thread group; and

yielding the one or more of the processors to the second thread or thread group within the time limit without saving a context of the first thread or thread group if the first thread or thread group can wind up within the time limit, or performing a context switch from the first thread or thread group to the second thread or thread group if the first thread or thread group cannot wind up within the time limit.

2. A non-transitory computer-readable medium having a set of computer readable instructions embodied therein, the computer-readable instructions being configured to implement a method for a multi-threaded processing on a computer system having one or more processors coupled to a memory, the computer-readable instructions comprising:

one or more pre-emption-notification instructions that, when executed, notify one or more of the processors running a first thread or thread group of a pre-emption by a second thread or thread group characterized by a higher priority than the first thread or thread group;

one or more wait-time-notification instructions that, when executed, notify the first thread or thread group of a time limit for pre-emption associated with the second thread or thread group, wherein the time limit for pre-emption specifies how long the second thread or thread group can wait before preempting the first thread or thread group, wherein the time limit is less than a time needed for a context switch from the first thread or thread group to the second thread or thread group; and

one or more yield instructions that, when executed, yield the one or more of the processors to the second thread or thread group within the time limit without saving a context of the first thread or thread group if the processor can yield the first thread or thread group within the time limit or perform a context switch from the first thread or thread group to the second thread or thread group if the processor cannot yield the first thread or thread group within the time limit.

3. The computer-readable medium of claim 2 wherein the pre-emption-notification instructions are part of an operating system for the computer system.

4. The computer-readable medium of claim 2 wherein the wait-time-notification instructions are part of an operating system for the computer system.

5. The computer-readable medium of claim 2 wherein the yield instructions include one or more instructions that are part of an operating system for the computer system.

6. The computer-readable medium of claim 2 wherein the yield instructions include one or more instructions that, when executed, unlock a mutex previously locked by the first thread or thread group before yielding the one or more of the processors to the second thread or thread group.

7. The computer-readable medium of claim 2 wherein the yield instructions include one or more instructions that, when executed, maintain the first thread in a ready state until a subsequent call to execute the first thread or thread group.

8. The computer-readable medium of claim 2, wherein the computer-readable instructions further comprise one or more instructions that, when executed, group the first thread with one or more other threads in a group characterized by a thread group type, wherein the thread group type is either a constant-sized group of two or more threads that are gang-scheduled or a variable-sized group of two or more threads that can be scheduled and/or unscheduled one at a time.

9. The computer-readable medium of claim 8 wherein, if the thread group type is variable-sized, the yield instructions are configured to yield only the first thread and no other threads in the group if only the first thread is pre-empted.

10. The computer-readable medium of claim 8 wherein, if the thread group type is constant-sized, the yield instructions are configured to yield the first thread and all other threads in the group even if only the first thread is pre-empted.

11. The computer-readable medium of claim 2 wherein the context switch includes saving context data associated with the first thread in the memory.

12. The computer-readable medium of claim 2 wherein the yield instructions include one or more instructions that, when executed, schedule the second thread for execution on the one or more of the processors.

13. A computer system, comprising:

one or more processors; and

a memory coupled to the one or more processors,

wherein the computer system is programmed with a set of computer-readable instructions configured to implement a method for a multi-threaded processing, the computer-readable instructions comprising;

one or more pre-emption-notification instructions that, when executed, notify one or more of the processors running a first thread or thread group of a pre-emption by a second thread or thread group characterized by a higher priority than the first thread or thread group;

one or more wait-time-notification instructions that, when executed, notify the one or more of the processors of a time limit for pre-emption associated with the second thread or thread group, wherein the time limit for pre-emption specifies how long the second thread or thread group can wait before preempting the first thread or thread group, wherein the time limit is less than a time needed for a context switch from the first thread or thread group to the second thread or thread group; and

one or more yield instructions that, when executed, yield the one or more of the processors to the second thread or thread group within the time limit without saving a context of the first thread or thread group if the one or more of the processors can yield the first thread or thread group within the time limit or perform a context switch from the first thread or thread group to the second thread or thread group if the one or more of the processors cannot yield within the time limit.

14. The computer system of claim 13 wherein the one or more processors include two or more processors.

15. The computer system of claim 14 wherein the two or more processors include a power processor element and one or more synergistic processor elements, wherein the power processing element is a conventional general purpose processing element configured to control a synergistic processing element and wherein the synergistic processor element includes a register and a local memory.

16. The computer system of claim 13 wherein the pre-emption-notification instructions are part of an operating system for the computer system.

17. The computer system of claim 13 wherein the wait-time-notification instructions are part of an operating system for the computer system.

18. The computer system of claim 13 wherein the yield instructions include one or more instructions that are part of an operating system for the computer system.

19. The computer system of claim 13 wherein the yield instructions include one or more instructions that, when executed, unlock a mutex previously locked by the first thread or thread group before yielding the one or more of the processors to the second thread.

20. The computer system of claim 13 wherein the yield instructions include one or more instructions that, when executed, maintain the first thread or thread group in a ready state until a subsequent call to execute the first thread.

21. The computer system of claim 13, wherein the computer-readable instructions further comprise one or more instructions that, when executed, group the first thread with one or more other threads in a group characterized by a thread group type, wherein the thread group type is either a constant-sized group of two or more threads that are gang-scheduled or a variable-sized group of two or more threads that can be scheduled and/or unscheduled one at a time.

22. The computer system of claim 21 wherein, if the thread group type is variable-sized, the yield instructions are configured to yield only the first thread and no other threads in the group if only the first thread is pre-empted.

23. The computer system of claim 21 wherein, if the thread group type is constant-sized, the yield instructions are configured to yield the first thread and all other threads in the group even if only the first thread is pre-empted.

24. The computer system of claim 13 wherein the context switch includes saving context data associated with the first thread or thread group in the memory.

25. The computer system of claim 13 wherein the yield instructions include one or more instructions that, when executed, schedule the second thread or thread group for execution on the one or more of the processors.

26. The computer system of claim 13 wherein the one or more processors include a power processing element and one or more synergistic processing elements, wherein the power processing element is a conventional general purpose processing element configured to control a synergistic processing element and wherein the synergistic processor element includes a register and a local memory.

27. The computer system of claim 13 wherein the one or more processors include a multi-core processor.

28. The computer system of claim 13 wherein the system is a component of a personal computer, laptop computer, hand held internet browser device, hand-held email device, Voice over Internet Protocol (VoIP) phones, video game console, or hand-held video game device.

29. The computer system of claim 28 wherein the one or more processors include a power processing element and one or more synergistic processing elements and the device is a video game console, wherein the power processing element is a conventional general purpose processing element configured to control a synergistic processing element and wherein the synergistic processor element includes a register and a local memory.

30. The computer system of claim 13 wherein the one or more processors include an asymmetric multi-core processor.

31. The computer system of claim 30 wherein the multi-core processor includes one or more limited cores of a type that cannot perform a full thread context switch on itself.

32. The computer system of claim 31 wherein, if a context switch is required for one or more of the limited cores, one or more remaining cores of the multi-core processor must perform context switches in full or in part on behalf of the one or more limited cores requiring the context switch.

33. The computer system of claim 32 wherein a context switch of the limited core processor results in undesired overhead for the computer system.