Low temperature fabrication of lateral thin film varistor

• US 9,870,851 B2
• Filed: 05/09/2016
• Issued: 01/16/2018
• Est. Priority Date: 02/26/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Graf, Richard S., Mandal, Sudeep
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US15/149,652
• Publication Number:
  US 20160254344A1
• Time in Patent Office: 617 Days
• Field of Search: None
• CPC Class Codes: H01C 17/006 adapted for manufacturing resistor chips
• CPC Class Codes: H01C 17/06553 composed of a combination of metals and oxides
• CPC Class Codes: H01C 17/12 by sputtering
• CPC Class Codes: H01C 17/245 by mechanical means, e.g. sand blasting, cutting, ultrasonic treatment
• CPC Class Codes: H01C 17/288 by thin film techniques
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01C 7/1013 Thin film varistors
• CPC Class Codes: H01C 7/108 Metal oxide
• CPC Class Codes: H01C 7/112 ZnO type
• CPC Class Codes: H01C 7/12 Overvoltage protection resistors series resistors structurally associated with spark gaps H01T1/16
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 28/24 : with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Claims

1. A lateral thin film varistor device, comprising:

a substrate;

a first dielectric layer on the substrate;

a second dielectric layer on the first dielectric layer;

a continuous, varistor layer on the second dielectric layer and comprising alternating regions of a first metal oxide layer and a second metal oxide layer located between, and in contact with, two laterally spaced electrodes for lateral flow of transient voltages; and

a third dielectric layer on said continuous, varistor layer.

2. The lateral thin film varistor device according to claim 1, wherein the third dielectric layer is directly on said continuous, varistor layer.

3. The lateral thin film varistor device according to claim 1, further comprising:

an isolation layer between the second and third dielectric layers, and wherein;

the continuous, varistor layer is positioned in said isolation layer; and

the third dielectric layer is directly on the isolation layer and the continuous, varistor layer.

4. The lateral thin film varistor device according to claim 1, further comprising a capping layer interposed between the first and second dielectric layers.

5. A lateral thin film varistor device according to claim 1, further comprising a top capping layer on the third dielectric layer.

6. A lateral thin film varistor device according to claim 1, further comprising a plurality of electrically conductive vias in the third dielectric layer and in electrical contact with the two electrodes.

7. A lateral thin film varistor device according to claim 1, wherein the third dielectric layer laterally extends past the alternating regions of the first and second metal oxide layers.

8. A lateral thin film varistor device according to claim 1, further comprising an electrically conductive interconnect extending through the third dielectric layer.

9. A lateral thin film varistor device according to claim 1, further comprising a plurality of electrically conductive lines in the third dielectric layer.

10. A lateral thin film varistor device according to claim 1, wherein the third dielectric layer laterally extends over the two electrodes.

11. A method of forming a lateral thin film varistor device, comprising:

forming a continuous, varistor layer comprising alternating regions of a first metal oxide layer and a second metal oxide layer between two laterally spaced electrodes for lateral flow of transient voltages, and using a sputtering process followed by an annealing process, including forming the continuous, varistor layer above separate first and second dielectric layers; and

forming a third dielectric layer on said continuous, varistor layer.

12. The method according to claim 11, wherein the forming a third dielectric layer includes forming the third dielectric layer directly on the continuous, varistor layer.

13. The method according to claim 12, further comprising:

forming an isolation layer between the second and third dielectric layers, and wherein;

the forming a continuous varistor layer includes forming the continuous, varistor layer in said isolation layer.

14. The method according to claim 11, further comprising:

forming a capping layer above the first dielectric layer; and

wherein;

the second dielectric layer is on said capping layer.

15. The method according to claim 11, further comprising forming a top cap layer on the third dielectric layer.

16. A lateral thin film varistor device, comprising:

a substrate;

a first dielectric layer on the substrate;

a capping layer on the first dielectric layer

a second dielectric layer on the first dielectric layer;

an isolation layer on the second dielectric layer;

a continuous, varistor layer in the isolation layer, above the second dielectric layer and comprising alternating regions of a first metal oxide layer and a second metal oxide layer located between, and in contact with, two laterally spaced electrodes; and

a third dielectric layer on said continuous, varistor layer.

17. The lateral thin film varistor device according to claim 16, wherein the third dielectric layer is directly on said continuous, varistor layer.

18. The lateral thin film varistor device according to claim 16, wherein the third dielectric layer is directly on said isolation layer.

19. The lateral thin film varistor device according to claim 16, wherein the laterally spaced electrodes directly contact regions of the first metal oxide layer.

20. The lateral thin film varistor device according to claim 16, wherein the third dielectric layer laterally extends past the alternating regions of the first and second metal oxide layers and laterally over the two electrodes.