Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of AACNT-TS via opens
First Claim
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1. A method for making integrated circuits (ICs), comprising at least:
- (a) performing initial processing steps to produce a test wafer that includes a first Design of Experiments (DOE) of Non-Contact Electrical Measurement (NCEM)-enabled, source/drain contact (AACNT)-source/drain silicide (TS)-via-open-configured fill cells, said initial processing steps including;
(i) patterning, on the test wafer, a first means for enabling NC detection of AACNT-TS via opens; and
,(ii) patterning, on the test wafer, a second means for enabling NC detection of AACNT-TS via opens;
wherein the first and second means for enabling NC detection of AACNT-TS via opens are different;
(b) determining a presence or absence of AACNT-TS via opens on the test wafer by;
performing a voltage contrast examination of NCEM-enabled fill cells in the first DOE, including at least the first and second means for enabling NC detection of AACNT-TS via opens; and
,(c) using the results from step (b) to select NCEM-enabled fill cells for inclusion on a subsequent product wafer.
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Abstract
Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of AACNT-TS via opens.
102 Citations
14 Claims
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1. A method for making integrated circuits (ICs), comprising at least:
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(a) performing initial processing steps to produce a test wafer that includes a first Design of Experiments (DOE) of Non-Contact Electrical Measurement (NCEM)-enabled, source/drain contact (AACNT)-source/drain silicide (TS)-via-open-configured fill cells, said initial processing steps including; (i) patterning, on the test wafer, a first means for enabling NC detection of AACNT-TS via opens; and
,(ii) patterning, on the test wafer, a second means for enabling NC detection of AACNT-TS via opens; wherein the first and second means for enabling NC detection of AACNT-TS via opens are different; (b) determining a presence or absence of AACNT-TS via opens on the test wafer by; performing a voltage contrast examination of NCEM-enabled fill cells in the first DOE, including at least the first and second means for enabling NC detection of AACNT-TS via opens; and
,(c) using the results from step (b) to select NCEM-enabled fill cells for inclusion on a subsequent product wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14)
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13. A method for making ICs, comprising at least:
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(a) performing initial processing steps to produce a test wafer that includes a first DOE of NCEM-enabled, AACNT-TS-via-open-configured fill cells, said initial processing steps including; (i) patterning, on the test wafer, a first means for enabling NC detection of AACNT-TS via opens; and
,(ii) patterning, on the test wafer, a second means for enabling NC detection of AACNT-TS via opens; wherein the first and second means for enabling NC detection of AACNT-TS via opens are different; (b) determining a presence or absence of AACNT-TS via opens on the test wafer by; performing a voltage contrast examination of NCEM-enabled fill cells in the first DOE, including at least the first and second means for enabling NC detection of AACNT-TS via opens; and
,(c) using the results from step (b) in processing of a subsequent product wafer.
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Specification
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InventorsLam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
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Primary Examiner(s)Henry, Caleb
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Assistant Examiner(s)Belousov, Alexander
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Application NumberUS15/281,508Time in Patent Office473 DaysField of SearchUS Class CurrentCPC Class CodesG01R 31/2884 using dedicated test connec...G06F 11/079 Root cause analysis, i.e. e...G06F 30/30 Circuit designG06F 30/39 Circuit design at the physi...G06F 30/392 Floor-planning or layout, e...G06F 30/398 Design verification or opti...H01L 2027/11866 Gate electrode terminals or...H01L 2027/11875 Wiring region, routingH01L 2027/11885 Two levels of metalH01L 2027/11887 Three levels of metalH01L 22/20 Sequence of activities cons...H01L 22/26 Acting in response to an on...H01L 22/34 Circuits for electrically c...H01L 23/5226 Via connections in a multil...H01L 23/528 Geometry or layout of the i...H01L 27/0207 Geometrical layout of the c...H01L 27/11803 using field effect technologyH01L 27/11807 CMOS gate arraysH01L 29/0649 Dielectric regions, e.g. Si...H01L 29/0684 characterised by the shape,...View All
