Method and apparatus for routing die signals using external interconnects

• US 9,871,012 B2
• Filed: 03/14/2013
• Issued: 01/16/2018
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Srinivas, Vaishnav, Yang, Bernie Jord, Brunolli, Michael, West, David Ian, Paynter, Charles David
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): KHAN, FARID H
• Application Number:
  US13/802,759
• Publication Number:
  US 20140061642A1
• Time in Patent Office: 1,769 Days
• Field of Search: 438106, 257 48, 257737, 257786
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/13028 the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/14165 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/27462 Electroplating
• CPC Class Codes: H01L 2224/29028 the layer connector being disposed on at least two separate bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/29078 being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/29147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/3012 : Layout
• CPC Class Codes: H01L 2224/3213 : the layer connector connecting within a semiconductor or solid-state body, i.e. connecting two bonding areas on the same semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/831 : the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Claims

1. An apparatus comprising:

a die comprising an interior portion and an exterior portion, wherein the interior portion comprises;

a first circuit formed in a first area of the interior portion;

a second circuit formed in a second area of the interior portion; and

a third circuit formed in a third area of the interior portion, the first circuit separate from the second circuit or the third circuit; and

wherein the exterior portion comprises;

a first trace coupling the first circuit to a first conductive structure supported by the exterior portion of the die;

a second trace coupling the second circuit to a second conductive structure supported by the exterior portion of the die; and

a third trace coupling the third circuit to a third conductive structure supported by the exterior portion of the die; and

a package encasing the die and supporting, via an internal surface of the package, an interconnect layer that is external to the die, the interconnect layer electrically connecting the first, second, and third conductive structures effective to distribute signals generated by the first circuit to the second and third circuits, the signals generated by the first circuit remaining within the package encasing the die.

2. The apparatus of claim 1, wherein the interconnect layer comprises copper or aluminum.

3. The apparatus of claim 1, wherein the interconnect layer is configured to support respective contacts that facilitate the electrical connection of the interconnect layer with the first and second conductive structures.

4. The apparatus of claim 3, wherein the conductive structures comprise copper pillars or copper cylinders.

5. The apparatus of claim 1, wherein the first trace or the second trace of the die comprises a first thickness, the interconnect layer comprises a second thickness, and the second thickness of the interconnect layer is at least 5 times thicker than the first thickness of the first trace or the second trace of the die.

6. The apparatus of claim 1, wherein the interconnect layer is supported by an interior surface of the package.

7. The apparatus of claim 6, wherein the interconnect layer comprises a layer of conductive material formed on the interior surface of the package.

8. The apparatus of claim 6, wherein the signals generated by the first circuit are distributed to the second circuit and remain between the die and the interior surface of the package.

9. The apparatus of claim 6, wherein the signals generated by the first circuit are distributed to the second circuit and remain within the package completely covering the die.

10. The apparatus of claim 1, wherein the first trace and the second trace reside on a routing layer of the die.

11. The apparatus of claim 1, wherein the first circuit is configured to generate a signal and the second circuit is configured to consume the signal.

12. The apparatus of claim 11, wherein the signal is a clock signal and the first circuit comprises a clock circuit or a clock generator configured to generate the clock signal.

13. The apparatus of claim 1, wherein the interior portion of the die further comprises a testing circuit configured to couple the first and second circuits during a testing mode.

14. The apparatus of claim 13, wherein the testing circuit comprises a multiplexer configured to allow selection between the testing circuit and the interconnect layer to couple the first and second circuits.

15. The apparatus of claim 13, wherein the testing circuit that couples the first and second circuits operates at a frequency less than that of signals communicated by the interconnect layer.

16. The apparatus of claim 13, wherein the testing circuit is inoperable to couple the first circuit to the second circuit other than during the testing mode.

17. An apparatus comprising:

a die comprising an interior portion and an exterior portion, wherein the interior portion comprises;

a first circuit formed in a first area of the interior portion;

a second circuit formed in a second area of the interior portion, the first circuit separate from the second circuit; and

a third circuit formed in a third area of the interior portion, the first circuit separate from the second circuit or the third circuit;

first and second contact means supported by the exterior portion of the die;

a first trace coupling the first circuit to the first contact means supported by the exterior portion of the die;

a second trace coupling the second circuit to the second contact means supported by the exterior portion of the die;

a third trace coupling the third circuit to a third conductive structure supported by the exterior portion of the die; and

a casing that contains the die and supporting contact pins and interconnect means for electrically connecting the first and second contact means effective to couple the first circuit and the second circuit of the interior portion of the die, the contact pins configured to connect signals of the die to circuits external to both the die and the casing.

18. The apparatus of claim 17, wherein the interconnect means comprises copper or aluminum.

19. The apparatus of claim 17, wherein the interconnect means comprises an interconnection layer having respective electrical contacts that facilitate the electrical connection of the interconnect means with the first and second contact means of the die.

20. The apparatus of claim 17, wherein the first and second contact means are formed as metallic pillars or cylinders.

21. The apparatus of claim 17, wherein the first trace or the second trace of the die comprises a first thickness, the interconnect means comprises a second thickness, and the second thickness of the interconnect means is at least 5 times thicker than the first thickness of the first trace or the second trace of the die.

22. The apparatus of claim 17, wherein the interconnect means comprises a layer of conductive material formed on an interior surface of the casing.

23. The apparatus of claim 17, wherein signals generated by the first circuit are distributed to the second circuit and remain between the die and an interior surface of the casing completely covering the die.

24. The apparatus of claim 17, wherein signals generated by the first circuit are distributed to the second circuit and remain within the casing completely covering the die.

25. The apparatus of claim 17, wherein at least one of the first and second contact means comprise a copper pillar supported by an under-bump metallization layer of the die.

26. The apparatus of claim 17, wherein the first trace and the second trace reside on a routing layer of the die.

27. The apparatus of claim 17, wherein the first circuit comprises means for generating a signal and the second circuit is configured to consume the signal.

28. The apparatus of claim 17, wherein the interior portion of the die further comprises testing means configured to couple the first and second circuits during a testing mode.

29. The apparatus of claim 28, wherein the testing means comprises a multiplexer configured to allow selection between a testing circuit and the interconnect means to couple the first and second circuits.

30. The apparatus of claim 28, wherein the testing means that couples the first and second circuits operates at a frequency less than that of signals communicated by the interconnect means.

31. The apparatus of claim 28, wherein the testing means is inoperable to couple the first circuit to the second circuit other than during the testing mode.