Flipped die stack assemblies with leadframe interconnects

• US 9,871,019 B2
• Filed: 07/13/2016
• Issued: 01/16/2018
• Est. Priority Date: 07/17/2015
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Prabhu, Ashok S., Katkar, Rajesh, Wang, Liang, Uzoh, Cyprian Emeka
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US15/209,034
• Publication Number:
  US 20170018485A1
• Time in Patent Office: 552 Days
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/1436 Dynamic random-access memory [DRAM]

Abstract

A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.

Claims

1. A microelectronic assembly, comprising:

a chip stack comprising a plurality of microelectronic elements having front surfaces, each front surface defining a respective plane of a plurality of planes, each microelectronic element having a plurality of contacts at the front surface and an edge surface extending away from its front surface, and a dielectric region on an edge surface of the respective microelectronic element, the dielectric region having a remote surface displaced in a lateral direction beyond the edge surface of the respective microelectronic element;

a plurality of leadframe interconnects each electrically coupled to a contact on one of the microelectronic elements and each having an end at the remote surface of the dielectric region of the respective microelectronic element;

a support element having a plurality of electrically conductive contacts insulated from one another at a major surface thereof, the major surface defining a second plane non-parallel to the plurality of parallel planes, wherein the chip stack is mounted to the support element with the remote surfaces of the dielectric regions towards the major surface and the leadframe interconnects facing and joined with corresponding contacts at the major surface.

2. The microelectronic assembly as claimed in claim 1, wherein a plurality of the chip stacks are mounted to the support element at a separation of at least 100 microns between first and second adjacent chip stacks.

3. The microelectronic assembly as claimed in claim 1, wherein the leadframe is a molded leadframe.

4. The microelectronic assembly as claimed in claim 1, wherein the ends of the leadframe interconnects coupled to the respective microelectronic element extend beyond the remote surface of the dielectric region on the edge surface of the respective microelectronic element.

5. The microelectronic assembly as claimed in claim 1, wherein the ends of the leadframe interconnects coupled to the respective microelectronic element are flush with or recessed relative to the remote surface of the dielectric region on the edge surface of the respective microelectronic element.

6. The microelectronic assembly as claimed in claim 5, wherein the ends of the leadframe interconnects coupled to the respective microelectronic element are disposed between the dielectric region extending from the respective microelectronic element and the dielectric region extending from the microelectronic element adjacent to the respective microelectronic element.

7. The microelectronic assembly as claimed in claim 1, wherein the leadframe interconnects are metallurgically joined with the contacts on the respective microelectronic element through electrically conductive bumps consisting essentially of gold, nickel, tin or copper.

8. The microelectronic assembly as claimed in claim 1, further comprising metal superstructures deposited by a process including plating onto the contacts, each superstructure comprising a layer consisting essentially of copper and projecting at least 5 microns above the surface of the support element, wherein the leadframe interconnects are metallurgically joined directly to the metal superstructures, or are joined to the metal superstructures with an electrically conductive bond material.

9. The microelectronic assembly as claimed in claim 8, wherein the metal superstructures have areas defined by areas of major surfaces of the contacts.

10. A microelectronic assembly, comprising:

a chip stack comprising a plurality of microelectronic elements having front surfaces, each front surface defining a respective plane of a plurality of planes, each microelectronic element having a plurality of contacts at the front surface and an edge surface extending away from its front surface in a first direction transverse to its front surface, and a dielectric region overlying an edge surface of the respective microelectronic element, the dielectric region extending from the edge surface in a second direction transverse to the edge surface to a remote surface displaced in the second direction beyond the edge surface of the respective microelectronic element;

a plurality of leadframe interconnects each electrically coupled to a contact on one of the microelectronic elements and each having an end at the remote surface of the dielectric region of the respective microelectronic element;

a support element having a plurality of electrically conductive contacts insulated from one another at a major surface thereof, the major surface defining a second plane non-parallel to the plurality of parallel planes, wherein the chip stack is mounted to the support element with the remote surfaces of the dielectric regions towards the major surface and the leadframe interconnects facing and joined with corresponding contacts at the major surface.

11. The microelectronic assembly as claimed in claim 10, wherein the remote surface of the dielectric region of each of the microelectronic elements is closer to the major surface of the support element than the edge surface of the respective microelectronic element.

12. The microelectronic assembly as claimed in claim 10, further comprising a reinforcing underfill material surrounding individual connections between the leadframe interconnects and the contacts of the support element.

13. The microelectronic assembly as claimed in claim 12, wherein each of the dielectric regions extends at least partially into the reinforcing underfill material in the second direction.