Semiconductor device and structure

• US 9,871,034 B1
• Filed: 12/30/2012
• Issued: 01/16/2018
• Est. Priority Date: 12/29/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US13/731,108
• Time in Patent Office: 1,843 Days
• Field of Search: 257278, 257355, 257360
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; and a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, and the second layer overlying the at least one metal layer; wherein the material composition of at least one of the plurality of second single crystal transistors is substantially different than the material composition of at least one of the plurality of first transistors.

Claims

1. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors; and

a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;

a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; and

a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors;

wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid.

2. The Integrated Circuit device according to claim 1, comprising at least one conductive layer underneath said second single crystal transistors,

wherein said at least one conductive layer comprises a plurality of strips controlled by at least one of said plurality of second single crystal transistors.

3. The Integrated Circuit device according to claim 1,

wherein said second layer comprises at least one buffer used to buffer a signal in-between at least two of said plurality of first transistors.

4. The Integrated Circuit device according to claim 1, comprising at least one thermal conducting path from at least one of said plurality of second single crystal transistors to a heat sink,

wherein said thermal conducting path comprises a thermal conductivity greater than 10 W/m-K.

5. The Integrated Circuit device according to claim 1, wherein said plurality of second single crystal transistors is aligned to said plurality of first transistors with less than 100 nm alignment error.

6. The Integrated Circuit device according to claim 1, wherein said second layer comprises at least one conductive pad for connecting power from outside of said device to said second conductive grid.

7. The Integrated Circuit device according to claim 1,

wherein said second transistors comprise self-aligned LDD.

8. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;

a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; and

a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors;

wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid, and

wherein said second layer comprises a wireless structure providing wireless communication between said device and external devices.

9. The Integrated Circuit device according to claim 8, comprising at least one conductive layer underneath said second single crystal transistors,

wherein said at least one conductive layer comprises a plurality of strips controlled by at least one of said plurality of second single crystal transistors.

10. The Integrated Circuit device according to claim 8, wherein said wireless structure is aligned to said plurality of first transistors with less than 100 nm alignment error.

11. The Integrated Circuit device according to claim 8,

wherein said second transistors comprise self-aligned LDD.

12. The Integrated Circuit device according to claim 8,

wherein at least one of said plurality of second single crystal transistors comprises a second material composition and at least one of said plurality of first transistors comprises a first material composition, and

wherein said second material composition is substantially different than said first material composition.

13. The Integrated Circuit device according to claim 8,

wherein said second layer comprises at least one conductive pad for connecting power to said device.

14. The Integrated Circuit device according to claim 8, further comprising:

a high quality oxide, said high quality oxide adapted for isolating at least two of said second transistors,

wherein said high quality oxide isolation has a leakage current of less than one picoamp per micron at device power supply and 25 degrees C.

15. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;

wherein said second layer comprises SerDes circuits, and

a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors;

a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors,

wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid; and

a connection path between at least one of said second transistors and at least one of said first transistors,

wherein said connection path comprises a through said second layer via with a diameter of 150 nm or less.

16. The Integrated Circuit device according to claim 15, comprising at least one conductive layer underneath said second single crystal transistors, said at least one conductive layer comprises a plurality of strips controlled by at least one of said plurality of second single crystal transistors.

17. The Integrated Circuit device according to claim 15, further comprising:

a high quality oxide, said high quality oxide adapted for isolating at least two of said second transistors,

wherein said high quality oxide isolation has a leakage current of less than one picoamp per micron at device power supply and 25 degrees C.

18. The Integrated Circuit device according to claim 15, comprising at least one thermal conducting path from at least one of said plurality of second single crystal transistors to a heat sink,

wherein said thermal conducting path comprises a thermal conductivity greater than 10 W/m-K.

19. The Integrated Circuit device according to claim 15,

wherein at least one of said plurality of second single crystal transistors comprises a second material composition and at least one of said plurality of first transistors comprises a first material composition, and

wherein said second material composition is substantially different than said first material composition.

20. The Integrated Circuit device according to claim 15,

wherein said second transistors comprise self-aligned LDD.