Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors

• US 9,871,041 B1
• Filed: 06/30/2016
• Issued: 01/16/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Liu, Zuoguang, Mehta, Sanjay C., Yamashita, Tenko
• Primary Examiner(s): WHALEN, DANIEL B
• Application Number:
  US15/199,544
• Publication Number:
  US 20180006036A1
• Time in Patent Office: 565 Days
• Field of Search: None
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a fin field effect transistor (finFET) with a doped substrate region, including forming a plurality of vertical fins on a substrate, forming a first dopant source on one or more of the plurality of vertical fins, wherein the first dopant source is not formed on at least one vertical fin, forming a second dopant source on the at least one vertical fin that does not have a first dopant source formed thereon, and heat treating the plurality of vertical fins on the substrate, the first dopant source, and the second dopant source, wherein the heat treatment is sufficient to cause a first dopant from the first dopant source to diffuse into at least a first portion of the substrate, and a second dopant from the second dopant source to diffuse into at least a second portion of the substrate.

Claims

1. A method of forming a fin field effect transistor (finFET) with a doped substrate region, comprising:

forming a plurality of vertical fins on a substrate;

forming a first dopant source on one or more of the plurality of vertical fins, wherein the first dopant source is not formed on at least one vertical fin;

forming a second dopant source on the at least one vertical fin that does not have the first dopant source formed thereon;

heat treating the plurality of vertical fins on the substrate, the first dopant source, and the second dopant source, wherein the heat treatment is sufficient to cause a first dopant from the first dopant source to diffuse into at least a first portion of the substrate to form a first punch-through stop/well extending about 10 nm to about 30 nm into the substrate from the interface with the first dopant source, and a second dopant from the second dopant source to diffuse into at least a second portion of the substrate to form a second punch-through stop/well extending about 10 nm to about 30 nm into the substrate from the interface with the second dopant source, wherein the concentration of the first dopant diffused into at least the first portion of the substrate is in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³, and the concentration of the second dopant diffused into at least the second portion of the substrate is in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³;

forming an isolation layer on the first dopant source and the second dopant source, wherein an upper portion of each of the plurality of vertical fins extends above the isolation layer; and

forming a gate dielectric layer on the upper portion of each of the plurality of vertical fins extending above the isolation layer, wherein the gate dielectric layer is formed by a conformal deposition.

2. The method of claim 1, wherein one of the first dopant or the second dopant is an n-type dopant, and the other of the first dopant or the second dopant is a p-type dopant.

3. The method of claim 1, wherein the first dopant source is phosphosilicate glass (PSG) or borosilicate glass (BSG).

4. The method of claim 3, wherein the material of the second dopant source is phospho-silicate glass (PSG) or boro-silicate glass (BSG), where the material of the second dopant source is different from the material of the first dopant source.

5. The method of claim 4, wherein the heat treatment is an annealing conducted at a temperature in the range of about 800°

C. to about 1000°

C.

6. The method of claim 5, wherein the heat treatment is conducted for a period of time in the range of about 30 seconds to about 150 minutes.

7. The method of claim 6, wherein the first dopant source is adjacent to the second dopant source, and the first dopant source and second dopant source have a height in the range of about 50 nm to about 150 nm.

8. The method of claim 1, wherein the first dopant also diffuses into the one or more of the plurality of vertical fins, and the second dopant also diffuses into the at least one vertical fin that does not have the first dopant source formed thereon.

9. A method of forming a fin field effect transistor (finFET) with a doped substrate region, comprising:

forming a plurality of vertical fins on a substrate by a sidewall image transfer process, where a first region of the substrate includes one or more vertical fin(s), and a second region of the substrate adjacent to the first region includes one or more vertical fin(s);

forming a first dopant source on the one or more vertical fin(s) in the first region;

forming a second dopant source on the one or more fin(s) in the second region, where the second dopant source is adjacent to and in contact with the first dopant source;

forming a capping layer on the first dopant source and the second dopant source;

heat treating the plurality of vertical fins on the substrate, the capping layer, the first dopant source, and the second dopant source, wherein the heat treatment is sufficient to cause a first dopant from the first dopant source to diffuse into at least a first portion of the substrate to form a first punch-through stop/well extending about 10 nm to about 30 nm into the substrate from the interface with the first dopant source, and a second dopant from the second dopant source to diffuse into at least a second portion of the substrate to form a second punch-through stop/well extending about 10 nm to about 30 nm into the substrate from the interface with the second dopant source, wherein the concentration of the first dopant diffused into at least the first portion of the substrate is in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³, and the concentration of the second dopant diffused into at least the second portion of the substrate is in the range of about 1×

10¹⁷/cm³ to about 1×

10¹⁹/cm³;

removing a portion of the capping layer from the first dopant source and the second dopant source to form an isolation layer on the first dopant source and the second dopant source that exposes an upper portion of each of the plurality of vertical fins extends above the isolation layer, wherein the isolation layer has a thickness in the range of about 5 nm to about 10 nm;

forming a gate dielectric layer on the upper portion of each of the plurality of vertical fins extending above the isolation layer in the first region and the second region, wherein the gate dielectric layer is formed by a conformal deposition.

10. The method of claim 9, wherein the second portion of the substrate at least partially overlaps the first portion of the substrate to form a compensated interface.

11. The method of claim 9, wherein the first dopant is boron and the second dopant is phosphorous.

12. The method of claim 9, wherein the first dopant and the second dopant are not aluminum, gallium, indium, or antimony.

13. The method of claim 9, wherein the first dopant source and the second dopant source are insulating glasses that form an isolation region between the one or more vertical fin(s) in the second region and the one or more vertical fin(s) in the first region, and the first dopant source and the second dopant source have a height in the range of about 50 nm to about 150 nm.

14. The method of claim 9, further comprising forming a first gate electrode layer on the one or more vertical fin(s) on the first region of the substrate, and forming a second gate electrode layer on the one or more vertical fin(s) on the second region of the substrate.