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Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors

  • US 9,871,041 B1
  • Filed: 06/30/2016
  • Issued: 01/16/2018
  • Est. Priority Date: 06/30/2016
  • Status: Active Grant
First Claim
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1. A method of forming a fin field effect transistor (finFET) with a doped substrate region, comprising:

  • forming a plurality of vertical fins on a substrate;

    forming a first dopant source on one or more of the plurality of vertical fins, wherein the first dopant source is not formed on at least one vertical fin;

    forming a second dopant source on the at least one vertical fin that does not have the first dopant source formed thereon;

    heat treating the plurality of vertical fins on the substrate, the first dopant source, and the second dopant source, wherein the heat treatment is sufficient to cause a first dopant from the first dopant source to diffuse into at least a first portion of the substrate to form a first punch-through stop/well extending about 10 nm to about 30 nm into the substrate from the interface with the first dopant source, and a second dopant from the second dopant source to diffuse into at least a second portion of the substrate to form a second punch-through stop/well extending about 10 nm to about 30 nm into the substrate from the interface with the second dopant source, wherein the concentration of the first dopant diffused into at least the first portion of the substrate is in the range of about 1×

    1017/cm3 to about 1×

    1019/cm3, and the concentration of the second dopant diffused into at least the second portion of the substrate is in the range of about 1×

    1017/cm3 to about 1×

    1019/cm3;

    forming an isolation layer on the first dopant source and the second dopant source, wherein an upper portion of each of the plurality of vertical fins extends above the isolation layer; and

    forming a gate dielectric layer on the upper portion of each of the plurality of vertical fins extending above the isolation layer, wherein the gate dielectric layer is formed by a conformal deposition.

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