Semiconductor device and method for manufacturing the same

• US 9,871,059 B2
• Filed: 12/07/2015
• Issued: 01/16/2018
• Est. Priority Date: 12/23/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Okazaki, Yutaka, Hanaoka, Kazuya, Sasagawa, Shinya, Kurata, Motomu
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US14/961,061
• Publication Number:
  US 20160093642A1
• Time in Patent Office: 771 Days
• Field of Search: 257 43, 257 57, 257290, 257 59, 257 72, 257184, 257257, 257258, 257291, 257293, 257347, 257443
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Claims

1. A semiconductor device comprising:

a first insulating layer including aluminum and oxygen;

an oxide semiconductor layer over the first insulating layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the gate insulating layer;

a second insulating layer in direct contact with a top surface of the gate electrode, a first side surface of the gate electrode and a second side surface of the gate electrode, the second insulating layer containing aluminum and oxygen;

a third insulating layer over the gate electrode, the third insulating layer containing silicon, oxygen and nitrogen;

a fourth insulating layer over the second insulating layer and the third insulating layer, the fourth insulating layer containing aluminum and oxygen;

a source electrode electrically connected to the oxide semiconductor layer; and

a drain electrode electrically connected to the oxide semiconductor layer,

wherein a distance between the gate electrode and a contact region in which the oxide semiconductor layer is in direct contact with the source electrode is greater than or equal to 1 nm and less than or equal to 30 nm.

2. The semiconductor device according to claim 1, wherein the fourth insulating layer is in direct contact with the second insulating layer.

3. The semiconductor device according to claim 1, further comprising:

the source electrode electrically connected to the oxide semiconductor layer; and

the drain electrode electrically connected to the oxide semiconductor layer,

wherein heights of top surfaces of the source electrode and the drain electrode are substantially the same as heights of top surfaces of the second insulating layer and the third insulating layer.

4. The semiconductor device according to claim 1, further comprising:

the source electrode electrically connected to the oxide semiconductor layer; and

the drain electrode electrically connected to the oxide semiconductor layer,

wherein heights of top surfaces of the source electrode and the drain electrode are substantially the same as heights of top surfaces of the second insulating layer and the third insulating layer, and

wherein a channel length of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 30 nm.

5. The semiconductor device according to claim 1,

wherein the semiconductor device further comprises a transistor including a semiconductor material having a band gap which is different from a band gap of the oxide semiconductor layer.

6. The semiconductor device according to claim 1,

wherein the semiconductor device is a memory cell.

7. The semiconductor device according to claim 1,

wherein the gate insulating layer is in direct contact with the oxide semiconductor layer, and

wherein the gate insulating layer contains excess oxygen.

8. The semiconductor device according to claim 1,

wherein the fourth insulating layer includes a first region and a second region,

wherein the first region overlaps the gate electrode,

wherein the second region does not overlap the oxide semiconductor layer,

wherein a distance between the first region and the first insulating layer is substantially the same as a distance between the second region and the first insulating layer.

9. A semiconductor device comprising:

a first insulating layer including aluminum and oxygen;

an oxide semiconductor layer over the first insulating layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the gate insulating layer;

a second insulating layer in direct contact with a top surface of the gate electrode, a first side surface of the gate electrode and a second side surface of the gate electrode, the second insulating layer containing aluminum and oxygen;

a third insulating layer over the gate electrode, the third insulating layer containing silicon, oxygen and nitrogen;

a fourth insulating layer over the second insulating layer and the third insulating layer, the fourth insulating layer containing aluminum and oxygen;

a source electrode electrically connected to the oxide semiconductor layer; and

a drain electrode electrically connected to the oxide semiconductor layer,

wherein a distance between the gate electrode and a contact region in which the oxide semiconductor layer is in direct contact with the source electrode is greater than or equal to 1 nm and less than or equal to 30 nm,

wherein the third insulating layer is in direct contact with a side surface of the second insulating layer.

10. The semiconductor device according to claim 9, wherein the fourth insulating layer is in direct contact with the second insulating layer.

11. The semiconductor device according to claim 9, further comprising:

the source electrode electrically connected to the oxide semiconductor layer; and

the drain electrode electrically connected to the oxide semiconductor layer,

wherein heights of top surfaces of the source electrode and the drain electrode are substantially the same as heights of top surfaces of the second insulating layer and the third insulating layer.

12. The semiconductor device according to claim 9, further comprising:

the source electrode electrically connected to the oxide semiconductor layer; and

the drain electrode electrically connected to the oxide semiconductor layer,

wherein heights of top surfaces of the source electrode and the drain electrode are substantially the same as heights of top surfaces of the second insulating layer and the third insulating layer, and

wherein a channel length of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 30 nm.

13. The semiconductor device according to claim 9,

wherein the semiconductor device further comprises a transistor including a semiconductor material having a band gap which is different from a band gap of the oxide semiconductor layer.

14. The semiconductor device according to claim 9,

wherein the semiconductor device is a memory cell.

15. The semiconductor device according to claim 9,

wherein the gate insulating layer is in direct contact with the oxide semiconductor layer, and

wherein the gate insulating layer contains excess oxygen.

16. The semiconductor device according to claim 9,

wherein the fourth insulating layer includes a first region and a second region,

wherein the first region overlaps the gate electrode,

wherein the second region does not overlap the oxide semiconductor layer,

wherein a distance between the first region and the first insulating layer is substantially the same as a distance between the second region and the first insulating layer.