Thin film transistor array substrate, method of manufacturing the same, and display device having the same

• US 9,871,062 B2
• Filed: 01/07/2016
• Issued: 01/16/2018
• Est. Priority Date: 04/21/2015
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Im, Wan Soon, Woo, Su Wan
• Primary Examiner(s): Nguyen, Sang V
• Application Number:
  US14/990,459
• Publication Number:
  US 20160315098A1
• Time in Patent Office: 740 Days
• CPC Class Codes: G02F 1/133528 Polarisers
• CPC Class Codes: G02F 1/133548 Wire-grid polarisers
• CPC Class Codes: G02F 1/133567 on the back side
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H10K 50/86 Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/8791 Arrangements for improving contrast, e.g. preventing reflection of ambient light

Abstract

A thin film transistor array substrate includes gate and data lines, a thin film transistor, a pixel electrode, a polarizing plate, and a contact line. The gate line is positioned on a base substrate, and disposed in a first direction. The data line is disposed in a second direction perpendicular to the first direction. The thin film transistor is connected to the gate and data lines. The pixel electrode is connected to the thin film transistor. The polarizing plate is positioned between the base substrate and the thin film transistor, and has a first metal pattern overlapping the thin film transistor on a plane, a second metal pattern overlapping the pixel electrode on a plane, and a third metal pattern overlapping the data line on a plane. The contact line is positioned over the data line, and connects the data line and the third metal pattern to each other.

Claims

1. A thin film transistor array substrate, comprising:

a first protective layer disposed on a base substrate;

a gate line disposed on the base substrate in a first direction;

a data line disposed in a second direction perpendicular to the first direction;

a thin film transistor connected to the gate line and the data line and disposed on the first protective layer;

a pixel electrode connected to the thin film transistor;

a polarizing plate disposed between the base substrate and the first protective layer, the polarizing plate comprising a first metal pattern overlapping the thin film transistor on a plane, a second metal pattern overlapping the pixel electrode on a plane, and a third metal pattern overlapping the data line on a plane; and

a contact line disposed over the data line, the contact line connecting the data line and the third metal pattern, a part of the contact line being directly disposed on the data line,

wherein the first metal pattern, the second metal pattern, and the third metal pattern are disposed on the same layer under the first protective layer, and

wherein the data line is electrically connected to the third metal pattern through the contact line and comprises a line of a double structure.

2. The thin film transistor array substrate of claim 1, wherein the first protective layer is disposed between the third metal pattern and the data line, and a second protective layer is disposed between the data line and the contact line.

3. The thin film transistor array substrate of claim 2, wherein the first protective layer comprises a first contact hole through which a portion of the third metal pattern is exposed, and the second protective layer comprises a second contact hole formed to correspond to a position of the first contact hole and a third contact hole through which the data line is exposed.

4. The thin film transistor array substrate of claim 3, wherein the contact line is in contact with the third metal pattern exposed through the first contact hole and the second contact hole, and in contact with the data line exposed through the third contact hole.

5. The thin film transistor array substrate of claim 4, wherein the data line and the third metal pattern are connected to each other through the contact line.

6. The thin film transistor array substrate of claim 1, wherein the contact line and the pixel electrode are disposed on the same layer and comprise the same conductive material.

7. The thin film transistor array substrate of claim 1, wherein the first to third metal patterns comprise the same conductive material.

8. The thin film transistor array substrate of claim 1, wherein the second metal pattern comprises a wire grid polarizer (WGP).

9. A method of manufacturing a thin film transistor array substrate, the method comprising:

disposing a polarizing plate comprising a first metal pattern, a second metal pattern, and a third metal pattern on a base substrate;

disposing, on the polarizing plate, a first protective layer comprising a first opening through which a portion of any one of the first to third metal patterns is exposed;

disposing, on the first protective layer, a gate line and a gate electrode extending from the gate line;

disposing, over the gate line and the gate electrode, a gate insulating layer comprising a second opening formed to correspond to a position of the first opening;

disposing, on the gate insulating layer, a semiconductor layer, a data line, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode;

disposing, over the data line, the source electrode, and the drain electrode, a second protective layer comprising a third opening formed to correspond to a position of the second opening, a fourth opening through which the data line is exposed, and a contact hole through which a portion of the drain electrode is exposed; and

disposing a pixel electrode connected to the drain electrode through the contact hole, and disposing a contact line in contact with the data line through the fourth opening and connected to the metal pattern exposed through the first to third openings.

10. The method of claim 9, wherein the first metal pattern overlaps the gate electrode, the source electrode, and the drain electrode on a plane, the second metal pattern overlaps the pixel electrode on a plane, and the third metal pattern overlaps the data line on a plane.

11. The method of claim 9, wherein the second metal pattern comprises a wire grid polarizer (WGP).

12. The method of claim 9, wherein the contact line overlaps the data line on a plane.

13. The method of claim 9, wherein the contact line is disposed on the same layer as the pixel electrode, and comprises the same conductive material.

14. A display device comprising:

a first protective layer disposed on a base substrate;

a gate line disposed on the base substrate in a first direction;

a data line disposed in a second direction perpendicular to the first direction;

a thin film transistor connected to the gate line and the data line and disposed on the first protective layer;

a display element connected to the thin film transistor and comprising a pixel electrode;

a polarizing plate disposed between the base substrate and the first protective layer, the polarizing plate comprising a first metal pattern overlapping the thin film transistor on a plane, a second metal pattern overlapping the pixel electrode on a plane, and a third metal pattern overlapping the data line on a plane; and

a contact line disposed over the data line along the second direction, the contact line electrically connecting the data line and the third metal pattern, a part of the contact line being directly disposed on the data line,

wherein the first metal pattern, the second metal pattern, and the third metal pattern are disposed on the same layer under the first protective layer, and

wherein the data line is electrically connected to the third metal pattern through the contact line and comprises a line of a double structure.

15. The display device of claim 14, further comprising the first protective layer being disposed between the third metal pattern and the data line, and a second protective layer disposed between the data line and the contact line,

wherein the first protective layer comprises a first contact hole through which a portion of the third metal pattern is exposed, and the second protective layer comprises a second contact hole formed to correspond to a position of the first contact hole and a third contact hole through which the data line is exposed.

16. The display device of claim 15, wherein the contact line is in contact with the third metal pattern exposed through the first contact hole and the second contact hole, and contacted with the data line exposed through the third contact hole.

17. The display device of claim 14, wherein the display element comprises a first electrode connected to the thin film transistor, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer.

18. The display device of claim 14, wherein the display element comprises a first electrode connected to the thin film transistor, a second electrode forming an electric field with the first electrode, and a liquid crystal layer driven by the electric field.