Semiconductor device with suppressed decrease in breakdown voltage of an insulation film and manufacturing method of the same

• US 9,871,098 B2
• Filed: 07/22/2015
• Issued: 01/16/2018
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Saito, Jun, Onogi, Atsushi, Aoi, Sachiko, Mizuno, Shoji
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): REIDA, MOLLY KAY
• Application Number:
  US15/516,837
• Publication Number:
  US 20170288014A1
• Time in Patent Office: 909 Days
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.

Claims

1. A semiconductor device comprising:

a semiconductor substrate in which a semiconductor element is provided; and

an insulation film provided on the semiconductor substrate,

wherein

the semiconductor substrate comprises a first portion and a second portion which has a thickness thinner than a thickness of the first portion, wherein an upper surface of the second portion is positioned lower than an upper surface of the first portion,

a recess extending in a thickness direction of the semiconductor substrate is provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin each other,

the insulation film extends over from the first portion to the second portion, and fills the recess,

a plurality of field limiting rings is provided in the second portion,

the field limiting ring which is nearest to the first portion is provided below the recess,

the field limiting rings are of a first conductivity type,

a trench is provided in the upper surface of the first portion,

a first region of the first conductivity type is provided in a vicinity of a bottom surface of the trench,

a second region of a second conductivity type exists between the field limiting ring which is the nearest to the first portion and the first region,

the bottom surface of the trench is located lower than a bottom surface of the recess, and

a distance from the bottom surface of the trench to the bottom surface of the recess in the thickness direction of the semiconductor substrate is shorter than a distance from the bottom surface of the recess to the upper surface of the second portion.

2. The semiconductor device according to claim 1, wherein

a width of the recess in a direction along which the first portion and the second portion adjoin each other is equal to or less than twice a thickness of the insulation film provided on the upper surface of the second portion.

3. The semiconductor device according to claim 1, wherein

an angle between a side surface of the recess on a second portion side and a side surface of the first portion is equal to or less than 90 degrees.

4. The semiconductor device according to claim 1, wherein

an angle between a side surface of the recess on a second portion side and a side surface of the first portion is equal to or less than 45 degrees.

5. The semiconductor device according to claim 1, wherein

a depth of the recess continuously increases toward the first portion.

6. A method of manufacturing a semiconductor device utilizing a semiconductor substrate that comprises a first portion and a second portion which has a thickness thinner than a thickness of the first portion, wherein an upper surface of the second portion is located lower than an upper surface of the first portion,

the method comprising:

forming a recess extending in a thickness direction of the semiconductor substrate on the upper surface of the second portion located at a position where the first portion and the second portion adjoin each other,

forming a plurality of field limiting rings, wherein a field limiting ring which is nearest to the first portion is formed below the recess by implanting impurities to the recess, and

forming, on the semiconductor substrate, an insulation film extending over from the first portion to the second portion and filling the recess, wherein

the field limiting rings are of a first conductivity type,

a trench is provided in the upper surface of the first portion,

a first region of the first conductivity type is provided in a vicinity of a bottom surface of the trench,

a second region of a second conductivity type exists between the field limiting ring which is the nearest to the first portion and the first region,

the bottom surface of the trench is located lower than a bottom surface of the recess, and

a distance from the bottom surface of the trench to the bottom surface of the recess in the thickness direction of the semiconductor substrate is shorter than a distance from the bottom surface of the recess to the upper surface of the second portion.