Bipolar semiconductor device with sub-cathode enhancement regions

• US 9,871,128 B2
• Filed: 03/18/2016
• Issued: 01/16/2018
• Est. Priority Date: 03/18/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Udrea, Florin, Camuso, Gianluca, Hsieh, Alice Pei-Shan, Ng, Chiu, Tang, Yi, Vytla, Rajeev Krishna, Li, Canhua
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US15/074,009
• Publication Number:
  US 20170271487A1
• Time in Patent Office: 669 Days
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

There are disclosed herein various implementations of a bipolar semiconductor device with sub-cathode enhancement regions. Such a bipolar semiconductor device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite the first conductivity type. The bipolar semiconductor device also includes first and second depletion trenches, each having a depletion electrode. In addition, the bipolar semiconductor device includes a first control trench situated between the first and second depletion trenches, the first control trench extending into the drift region and being adjacent to cathode diffusions. An enhancement region having the first conductivity type is localized in the drift region between the first control trench and one or both of the first and second depletion trenches. In one implementation, the bipolar semiconductor device may be an insulated-gate bipolar transistor (IGBT).

Claims

1. A bipolar semiconductor device comprising a plurality of unit cells, each of said plurality of unit cells comprising:

a drift region having a first conductivity type situated over an anode layer having a second conductivity type opposite said first conductivity type;

first and second depletion trenches, each having a depletion electrode;

a first control trench situated between said first and second depletion trenches, said first control trench extending into said drift region and being adjacent to cathode diffusions;

an enhancement region having said first conductivity type localized in said drift region between said first control trench and at least one of said first and second depletion trenches,

a third depletion trench adjacent to one of said first and second depletion trenches, wherein said enhancement region does not extend between said third depletion trench and either of said first and second depletion trenches,

wherein said first control trench extends deeper into said drift region than said enhancement region.

2. The bipolar semiconductor device of claim 1, wherein said enhancement region extends between said first control trench and each of said first and second depletion trenches.

3. The bipolar semiconductor device of claim 1, wherein a doping concentration of said enhancement region is greater than a doping concentration of said drift region.

4. The bipolar semiconductor device of claim 1, wherein a doping concentration of said enhancement region is less than a doping concentration of said cathode diffusions.

5. The bipolar semiconductor device of claim 1, wherein said depletion electrodes are electrically coupled to said cathode diffusions.

6. The bipolar semiconductor device of claim 1, wherein each of said plurality of unit cells further comprises a buffer layer having said first conductivity type situated between said anode layer and said drift region.

7. The bipolar semiconductor device of claim 1, wherein said first conductivity is N type and said second conductivity is P type.

8. The bipolar semiconductor device of claim 1, wherein each of said plurality of unit cells further comprises a second control trench situated between said first and second depletion trenches, said enhancement region extending between said second control trench and one of said first and second depletion trenches.

9. The bipolar semiconductor device of claim 8, wherein each of said plurality of unit cells further comprises a third depletion trench adjacent to one of said first and second depletion trenches, wherein said enhancement region does not extend between said third depletion trench and either of said first and second depletion trenches.

10. An insulated-gate bipolar transistor (IGBT) comprising a plurality of IGBT unit cells, each of said plurality of IGBT unit cells comprising:

a drift region having a first conductivity type situated over a collector having a second conductivity type opposite said first conductivity type;

first and second depletion trenches, each having a depletion electrode;

a first gate trench situated between said first and second depletion trenches, said first gate trench extending into said drift region and being adjacent to emitter diffusions;

an enhancement region having said first conductivity type localized in said drift region between said first gate trench and at least one of said first and second depletion trenches,

a third depletion trench adjacent to one of said first and second depletion trenches, wherein said enhancement region does not extend between said third depletion trench and either of said first and second depletion trenches,

wherein said first gate trench extends deeper into said drift region than said enhancement region.

11. The IGBT of claim 10, wherein said enhancement region extends between said first gate trench and each of said first and second depletion trenches.

12. The IGBT of claim 10, wherein a doping concentration of said enhancement region is greater than a doping concentration of said drift region.

13. The IGBT of claim 10, wherein a doping concentration of said enhancement region is less than a doping concentration of said emitter diffusions.

14. The IGBT of claim 10, wherein said depletion electrodes are electrically coupled to said emitter diffusions.

15. The IGBT of claim 10, wherein each of said plurality of IGBT unit cells further comprises a buffer layer having said first conductivity type situated between said collector and said drift region.

16. The IGBT of claim 10, wherein said first conductivity is N type and said second conductivity is P type.

17. The IGBT of claim 10, wherein each of said plurality of IGBT unit cells further comprises a second gate trench situated between said first and second depletion trenches, said enhancement region extending between said second gate trench and one of said first and second depletion trenches.

18. The IGBT of claim 17, wherein each of said plurality of IGBT unit cells further comprises a third depletion trench adjacent to one of said first and second depletion trenches, wherein said enhancement region does not extend between said third depletion trench and either of said first and second depletion trenches.