One-pass trigger jitter reduction for digital instruments

• US 9,874,587 B1
• Filed: 03/11/2016
• Issued: 01/23/2018
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Keysight Technologies, Inc.
• Inventors: Holcomb, Matthew S.
• Primary Examiner(s): Nguyen, Vinh
• Application Number:
  US15/068,315
• Time in Patent Office: 683 Days
• CPC Class Codes: G01R 13/0254 for triggering, synchronisation

Abstract

A system and method: receive an input signal and output digital samples representing the input signal; store the digital samples for at least one acquisition record of the input signal in an acquisition memory; detect a trigger event in the input signal and calculate a trigger address in the acquisition memory for a digital sample corresponding to the detected trigger event; perform digital signal processing on the digital samples of the acquisition memory to produce processed digital samples; detect an edge, representing a trigger, in the processed digital samples, and determine a measured trigger time; temporarily store the processed digital samples in a buffer memory at least until the edge detector detects the edge in the processed digital samples; determine a trigger correction value in response to the measured trigger time; determine a corrected beginning address of the buffer memory from the calculated trigger address and the trigger correction value; and read the processed digital data out from the buffer memory beginning at the corrected beginning address.

Claims

1. A system, comprising:

a signal acquisition subsystem configured to receive an input signal and in response thereto to output a plurality of digital samples representing the input signal;

an acquisition memory configured to receive the digital samples and to store therein the digital samples for at least one acquisition record of the input signal;

a trigger detector configured to detect a trigger event in the input signal and to calculate a trigger address in the acquisition memory for a digital sample corresponding to the detected trigger event in the input signal;

an acquisition memory read-out controller coupled to said trigger detector configured to control reading of the digital samples out of the acquisition memory;

a digital signal processor configured to receive the digital samples output from the acquisition memory under control of the acquisition memory read-out controller, and to process the digital samples to produce processed digital samples;

an edge detector configured to detect an edge, representing a trigger, in the processed digital samples, and in response thereto to determine and output a measured trigger time;

a buffer memory configured to temporarily store the processed digital samples output by the digital signal processor at least until the edge detector detects the edge in the processed digital samples;

a trigger correction value generator configured to receive the measured trigger time from the edge detector, and in response thereto to determine and output a trigger correction value; and

a buffer memory read-out controller configured to receive the trigger correction value and in response thereto to control reading of the processed digital samples out of the buffer memory beginning at a corrected beginning address of the buffer memory determined from the calculated trigger address and the trigger correction value.

2. The system of claim 1, further comprising a display device configured to display the processed digital samples beginning at the corrected beginning address of the buffer memory.

3. The system of claim 1, wherein the digital signal processor is configured to perform at least one of vertical scaling, inversion, random dithering, bandwidth shaping, and interpolation of the digital samples to produce the processed digital samples.

4. The system of claim 1, wherein the trigger correction value generator is further configured to provide the trigger correction value to the acquisition memory read-out controller.

5. The system of claim 4, further comprising:

a second signal acquisition subsystem configured to receive a second input signal and in response thereto to output a plurality of second digital samples representing the second input signal; and

a second acquisition memory configured to receive the second digital samples and to store therein the second digital samples for at least one acquisition record of the second input signal,

wherein the acquisition memory read-out controller is further configured to control reading of the second digital samples out of the second acquisition memory beginning at a corrected beginning address of the second acquisition memory determined from the calculated trigger address and the trigger correction value.

6. The system of claim 5, wherein the digital signal processor is further configured to receive the second digital samples output from the second acquisition memory in response to the acquisition memory read-out controller, and to process the second digital samples to produce second processed digital samples.

7. The system of claim 1, wherein the edge detector and the buffer memory are configured to receive the same processed digital samples at a same time as each other, and the buffer memory is configured to store at least all of the processed digital samples from the beginning of the acquisition record until the detected edge, representing the trigger, in the processed digital samples.

8. The system of claim 1, wherein the digital signal processor is configured to receive the digital samples from the acquisition memory in two channels, including a first channel of the digital samples starting at a beginning address of the acquisition record in the acquisition memory and a second channel operating in parallel with the first channel beginning at an address which is a defined number of addresses prior to the calculated trigger address, the digital signal processor further being configured to process the digital samples of the first channel and output the processed digital samples of the first channel to the buffer memory, and in parallel to process the digital samples of the second channel and output the processed digital samples of the second channel to the edge detector.

9. The system of claim 8, wherein the trigger correction value generator is further configured to provide the trigger correction value to the acquisition memory read-out controller, and wherein the system is configured to compare a size of the acquisition record to a threshold, and is further configured such that when the size of the acquisition record exceeds the threshold:

the digital signal processor switches to processing a single channel of the digital samples starting at a beginning address of the acquisition record in the acquisition memory and outputting the processed digital samples of the single channel to the edge detector; and

the acquisition memory read-out controller controls reading of the digital samples out of the acquisition memory a second time beginning at a corrected beginning address of the acquisition memory determined from the calculated trigger address and the trigger correction value.

10. The system of claim 8, wherein the trigger correction value generator is configured to determine the trigger correction value from only a subset of the processed digital samples from the digital signal processor which are in a defined range about the measured trigger time, excluding from the determination of the trigger correction value processed digital samples from the digital signal processor which are outside the defined range.

11. The system of claim 10, wherein a size of the buffer memory is approximately the same as the subset of the processed digital samples.

12. A method, comprising:

receiving an input signal and in response thereto outputting a plurality of digital samples representing the input signal;

storing the digital samples for at least one acquisition record of the input signal in an acquisition memory;

detecting a trigger event in the input signal and calculating a trigger address in the acquisition memory for a digital sample corresponding to the detected trigger event in the input signal;

performing digital signal processing on the digital samples output from the acquisition memory in response to an acquisition memory read-out controller to produce processed digital samples;

detecting an edge by an edge detector, representing a trigger, in the processed digital samples, and in response thereto determining and outputting a measured trigger time;

temporarily storing the processed digital samples output by the digital signal processor in a buffer memory at least until the edge detector detects the edge in the processed digital samples;

determining and outputting a trigger correction value in response to the measured trigger time from the edge detector;

determining a corrected beginning address of the buffer memory from the calculated trigger address and the trigger correction value; and

reading the processed digital data out from the buffer memory beginning at the corrected beginning address of the buffer memory.

13. The method of claim 12, further comprising displaying the processed digital samples on a display device, beginning at the corrected beginning address of the buffer memory.

14. The method of claim 12, further comprising receiving via a user interface one of more parameters for the display of the processed digital samples.

15. The method of claim 12, wherein performing the digital signal processing includes performing at least one of vertical scaling, inversion, random dithering, bandwidth shaping, and interpolation of the digital samples to produce the processed digital samples.

16. The method of claim 12, further comprising:

receiving a second input signal and in response thereto outputting a plurality of second digital samples representing the second input signal;

storing the second digital samples for at least one acquisition record of the second input signal in a second acquisition memory; and

reading the second digital samples out of the second acquisition memory beginning at a corrected beginning address of the second acquisition memory determined from a calculated trigger address and the trigger correction value.

17. The method of claim 16, further comprising processing the second digital samples to produce second processed digital samples.

18. The method of claim 12, further comprising storing in the buffer memory at least all of the processed digital samples from the beginning of the acquisition record until the detected edge, representing the trigger, in the processed digital samples.

19. The method of claim 12, further comprising processing the digital samples from the acquisition memory in parallel in two channels, including a first channel of the digital samples starting at a beginning address of the acquisition record in the acquisition memory and a second channel operating in parallel with the first channel beginning at an address which is a defined number of addresses prior to the calculated trigger address, and outputting the processed digital samples of the first channel to the buffer memory in parallel with outputting the processed digital samples of the second channel to an edge detector for detecting the edge, representing the trigger, in the processed digital samples within the subset of the processed digital samples.

20. The method of claim 19, further comprising comparing a size of the acquisition record to a threshold, and when the size of the acquisition record exceeds the threshold:

switching the digital signal processor to processing a single channel of the digital samples starting at a beginning address of the acquisition record in the acquisition memory, and outputting the processed digital samples of the single channel to the edge detector; and

reading the digital samples out of the acquisition memory a second time beginning at a corrected beginning address of the acquisition memory determined from the calculated trigger address and the trigger correction value.