Methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system

• US 9,875,152 B2
• Filed: 03/23/2015
• Issued: 01/23/2018
• Est. Priority Date: 10/05/2011
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Kessler, Martin
• Primary Examiner(s): Auve, Glenn A
• Application Number:
  US14/666,116
• Publication Number:
  US 20150301968A1
• Time in Patent Office: 1,037 Days
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 2213/0016 Inter-integrated circuit (I2C)
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: H04B 2203/5445 Local network
• CPC Class Codes: H04B 2203/547 via DC power distribution
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 3/548 the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02
• CPC Class Codes: H04B 3/56 Circuits for coupling, blocking, or by-passing of signals
• CPC Class Codes: H04L 12/40019 Details regarding a bus master
• CPC Class Codes: H04L 12/40026 Details regarding a bus guardian
• CPC Class Codes: H04L 12/40045 Details regarding the feeding of energy to the node from the bus
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/4035 in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

Claims

1. An electronic device configured for low latency communication on a communication bus, comprising:

first circuitry to;

communicate with at least one upstream device over a communication bus, wherein the at least one upstream device includes a master device,

periodically receive a synchronization control frame communicated downstream on the communication bus from the master device, and

transmit a synchronization response frame upstream on the communication bus, wherein the synchronization response frame originates at a last downstream device on the communication bus;

second circuitry to derive timing information from the synchronization control frame; and

third circuitry to, when a downstream device is coupled to the communication bus;

transmit the synchronization control frame downstream to the downstream device, and

receive the synchronization response frame from the downstream device.

2. The electronic device of claim 1, wherein the second circuitry is to generate the synchronization response frame when the electronic device is the last downstream device on the communication bus.

3. The electronic device of claim 1, wherein the first circuitry is to:

transmit data upstream on the communication bus, wherein the data is transmitted in at least one designated time interval following the synchronization control frame.

4. The electronic device of claim 3, wherein:

the data is first data;

the third circuitry is to, when the downstream device is coupled to the communication bus, receive second data from the downstream device; and

the first circuitry is to selectively transmit the second data upstream on the communication bus.

5. The electronic device of claim 4, wherein:

the third circuitry is to, when the downstream device is coupled to the communication bus, receive third data from the downstream device;

the second circuitry is to process the third data; and

the first circuitry is to not transmit the third data upstream.

6. The electronic device of claim 1, wherein the third circuitry is to:

transmit data downstream on the communication bus, wherein the data is transmitted in at least one designated time interval following the synchronization control frame.

7. The electronic device of claim 6, wherein:

the data is first data;

the first circuitry is to receive second data from the at least one upstream device; and

the third circuitry is to, when the downstream device is coupled to the communication bus, selectively transmit the second data downstream on the communication bus.

8. The electronic device of claim 1, wherein:

the first circuitry is to receive data from the at least one upstream device, the data including an identifier of the electronic device;

the second circuitry is to process the data; and

the third circuitry is to, when the downstream device is coupled to the communication bus, not transmit the data downstream based on the identifier.

9. The electronic device of claim 1, wherein:

the second circuitry is to generate data; and

the third circuitry is to, when the downstream device is coupled to the communication bus, transmit the data downstream.

10. The electronic device of claim 9, wherein the data includes an identifier of a downstream device that is to consume the data.

11. The electronic device of claim 1, wherein the second circuitry includes a phase locked loop (PLL), and the second circuitry is to, as part of derivation of timing information from the synchronization control frame, recover a clock signal from the synchronization control frame and provide that signal to the PLL.

12. The electronic device of claim 1, wherein the electronic device is a first electronic device, and wherein the first circuitry is to receive data from an upstream device and the second circuitry is to transmit the data to a second electronic device communicatively coupled to the first electronic device via an I2C bus.

13. The electronic device of claim 12, wherein:

the data is first data;

the first circuitry is to receive second data from the upstream device; and

the second circuitry is to transmit the second data to the second electronic device via an I2S bus.

14. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a sensor in a vehicle, and the electronic device is to provide data from the sensor over the communication bus for hands-free control of an in-vehicle function.

15. The electronic device of claim 14, wherein the sensor includes a microphone.

16. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a microphone in a vehicle, and the electronic device is to provide data from the microphone over the communication bus for voice control of an in-vehicle function.

17. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a sensor in a vehicle, and the electronic device is to provide data from the sensor over the communication bus to signal an emergency assistance system.

18. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a microphone, and the electronic device is to provide data from the microphone over the communication bus for active noise cancellation.

19. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a microphone, and the electronic device is to provide data from the microphone over the communication bus to provide an intercom function, a passenger-to-passenger communication function, or a driver-to-passenger communication function.

20. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a sensor in a vehicle, and the electronic device is to provide data from the sensor over the communication bus for beam-forming or beam-steering.

21. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a touchscreen device.

22. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to a user input device in a vehicle, and the electronic device is to provide data from the user input device over the communication bus for push-to-talk or audio mute functionality.

23. The electronic device of claim 1, wherein the electronic device is disposed in a seatbelt or a seat of a vehicle.

24. The electronic device of claim 23, wherein the electronic device is disposed in a stopper button of a seatbelt.

25. The electronic device of claim 1, wherein the first and third circuitry share a chip with a microelectromechanical system (MEMS) microphone.

26. The electronic device of claim 1, further comprising circuitry to perform time domain reflectometry (TDR) for line diagnostics upstream via the first circuitry or downstream via the third circuitry.

27. The electronic device of claim 1, further comprising a microelectromechanical system (MEMS) switch to pass power downstream from the electronic device.

28. The electronic device of claim 1, wherein the first and third circuitry is included in a die that is included in a stack of dies.

29. The electronic device of claim 1, further comprising a digital isolator to isolate the electronic device from another device.

30. The electronic device of claim 1, wherein the electronic device includes or is communicatively coupled to an accelerometer or a gyroscope, and the electronic device is to provide data from the accelerometer or the gyroscope over the communication bus.

31. The electronic device of claim 1, wherein the electronic device is to provide data secured by digital content protection over the communication bus.

32. The electronic device of claim 31, wherein the data secured by digital content protection includes High-Bandwidth Digital Content Protection (HDCP)-protected data or Digital Transmission Content Protection (DTCP)-protected data.

33. The electronic device of claim 1, wherein the electronic device includes a storage device and a processing device, and the first or third circuitry is to receive updated program code for storage in the storage device over the communication bus.

34. The electronic device of claim 33, wherein the storage device includes Flash memory.

35. The electronic device of claim 1, wherein the first or third circuitry is to receive Internet Protocol (IP) packets or compressed video frames over the communication bus.

36. The electronic device of claim 1, further comprising a switching regulator to step up or step down a supply voltage.

37. The electronic device of claim 36, wherein the switching regulator includes a switched capacitor voltage converter.

38. The electronic device of claim 1, wherein the electronic device is disposed in a rear-view mirror of a vehicle, a vehicle headliner, a vehicle restraint, or headrest of a vehicle.

39. The electronic device of claim 1, wherein a headend control unit is upstream of the electronic device on the communication bus, and the electronic device is coupled to or includes an amplifier in communication with the headend control unit via the communication bus.

40. A method for low latency communication on a communication bus, comprising:

communicating, by an electronic device, with at least one upstream device over a communication bus, wherein the at least one upstream device includes a master device;

periodically receiving, by the electronic device, a synchronization control frame communicated downstream on the communication bus from the master device;

transmitting, by the electronic device, a synchronization response frame upstream on the communication bus, wherein the synchronization response frame originates at a last downstream device on the communication bus;

deriving, by the electronic device, timing information from the synchronization control frame;

when a downstream device is coupled to the communication bus;

transmitting, by the electronic device, the synchronization control frame downstream to the downstream device; and

receiving, by the electronic device, the synchronization response frame from the downstream device.

41. The method of claim 40, further comprising:

reading, by the electronic device, a predetermined number of slots in a communication to the electronic device from the at least one upstream device, wherein the predetermined number of slots is based on a number of peripheral devices coupled to the electronic device.

42. The method of claim 40, further comprising:

generating, by the electronic device, data for upstream transmission at predetermined sampling times based on a sampling delay parameter provided to the electronic device by the master device to synchronize data sampling among multiple devices downstream of the master device.

43. The method of claim 40, wherein the communication bus is a two-wire bus.

44. The method of claim 43, wherein:

receiving the synchronization control frame and transmitting the synchronization response frame takes place over a first segment of the two-wire bus;

when the downstream device is coupled to the communication bus, transmitting the synchronization control frame and selectively receiving the synchronization response frame takes place over a second segment of the two-wire bus; and

the first and second segments are separate.

45. The method of claim 44, further comprising:

receiving, by the electronic device, power from an upstream device over the first segment of the two-wire bus; and

when the downstream device is coupled to the communication bus, selectively transmitting, by the electronic device, the power to the downstream device.

46. An electronic device configured for low latency communication over a communication bus, comprising:

means for communicating with at least one upstream device over a communication bus, wherein the at least one upstream device includes a master device;

means for periodically receiving a synchronization control frame communicated downstream on the communication bus from the master device;

means for transmitting a synchronization response frame upstream on the communication bus, wherein the synchronization response frame originates at a last downstream device on the communication bus;

means for deriving timing information from the synchronization control frame;

means for, when a downstream device is coupled to the communication bus, transmitting the synchronization control frame downstream to the downstream device; and

means for, when the downstream devices coupled to the communication bus, receiving the synchronization response frame from the downstream device.

47. The electronic device of claim 46, wherein the electronic device does not include a crystal oscillator for providing a clock for communication over the communication bus.

48. The electronic device of claim 46, wherein communication over the communication bus is half-duplex.