Network of memory systems

• US 9,875,205 B1
• Filed: 03/17/2014
• Issued: 01/23/2018
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Bruce, Ricardo H., Espuerta, Jarmie De La Cruz, Verdan, Marlon Basa
• Primary Examiner(s): Phan, Raymond
• Application Number:
  US14/217,161
• Time in Patent Office: 1,408 Days
• Field of Search: 710104-110, 710306-317, 710 20- 22, 710 29, 711147-153
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration

Abstract

A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.

Claims

1. An apparatus comprising:

a communication bus interface;

a flash memory module coupled to the communication bus interface via a communication bus;

a system controller coupled to the communication bus interface via an external communication bus; and

wherein the system controller performs a memory transaction via the communication bus interface to the flash memory module.

2. The apparatus of claim 1, wherein:

the flash memory module comprises a first flash memory module, said first flash memory module comprising;

a first flash array including a first plurality of flash memory devices and a first flash array controller coupled to the first flash array.

3. The apparatus of claim 1, wherein the system controller comprises a first system controller, said first system controller comprising:

a local bus interface;

an input/output device coupled to the local bus interface;

a processor coupled to the local bus interface; and

a memory module controller coupled to the local bus interface.

4. The apparatus of claim 1,

wherein the system controller comprises:

a first system controller;

wherein the apparatus further comprises a second system controller;

wherein the flash memory module comprises;

a first flash memory module and a second flash memory module;

wherein the first system controller can access a first plurality of flash memory devices in the flash memory module via the first the communication bus and a second plurality of flash memory devices in a second flash memory module via a second communication bus; and

wherein the second system controller can access a third plurality of flash memory devices in the first flash memory module via a third communication bus and a fourth plurality of flash memory devices in the second flash memory module via a fourth communication bus.

5. The apparatus of claim 3, wherein the memory module controller comprises a first memory module controller;

wherein the first memory module controller includes a bus controller and a direct memory access (DMA) controller.

6. The apparatus of claim 3,

wherein the memory module controller comprises a dual memory module controller;

wherein the dual memory module controller includes a first memory module controller and a second memory module controller, and a subcontroller/configuration device coupled to the dual memory module controller.

7. The apparatus of claim 4, wherein the first system controller comprises a first memory module controller configured to drive the first communication bus and a second memory module controller configured to drive the second communication bus;

wherein the second system controller comprises a third memory module controller configured to drive the third communication bus and a fourth memory module controller configured to drive the fourth communication bus;

wherein the first flash memory module comprises a first flash array controller coupled to the first communication bus and to the second communication bus; and

wherein the second flash memory module comprises a second flash array controller coupled to the third communication bus and to the fourth communication bus.

8. The apparatus of claim 5,

wherein the memory module controller includes an arbiter for processing an arbitration request from the DMA controller.

9. The apparatus of claim 6,

wherein the first memory module controller includes a first bus controller and a first direct memory access (DMA) controller;

wherein the second memory module controller includes a second bus controller and a second direct memory access (DMA) controller.

10. The apparatus of claim 9,

wherein the first memory module controller includes a first arbiter for processing an arbitration request from the first DMA controller;

wherein the second memory module controller includes a second arbiter for processing an arbitration request from the second DMA controller.

11. An apparatus comprising:

a plurality of flash memory modules interconnected with other flash memory modules and to a system controller via a point-to-point flashbus topology;

wherein the plurality of flash memory modules comprises a first flash memory module and a second flash memory module;

wherein the point-to-point flashbus topology comprises a first plurality of point-to-point lines and a second plurality of point-to-point lines;

wherein the system controller is coupled by the first plurality of point-to-point lines to the first flash memory module; and

wherein the first flash memory module is coupled by the second plurality of point-to-point lines to the second flash memory module.

12. The apparatus of claim 11, wherein the system controller comprises a first system controller, said first system controller comprising:

a local bus interface;

an input/output device coupled to the local bus interface;

a processor coupled to the local bus interface; and

a memory module controller coupled to the local bus interface.

13. The apparatus of claim 11, wherein the system controller is coupled to the first flash memory module by the first plurality of point-to-point lines comprising a first plurality of flashbus point-to-point lines and the first flash memory module is coupled to the second flash memory module by the second plurality of point-to-point lines comprising a second plurality of flashbus point-to-point lines.

14. The apparatus of claim 11, wherein the system controller is further coupled to the first flash memory module and second flash memory module by a plurality of flashbus shared lines.

15. The apparatus of claim 11, wherein the system controller comprises a first system controller;

wherein the apparatus further comprises a second system controller;

and

wherein the first system controller and second system controller are coupled to the first flash memory module and the first flash memory module is coupled to the second flash memory module.

16. The apparatus of claim 11,

wherein the system controller comprises a first system controller;

wherein the apparatus further comprises a second system controller;

wherein the first system controller and second system controller are coupled to the first flash memory module by a first plurality of flashbus point-to-point lines and the first flash memory module is coupled to the second flash memory module by a second plurality of flashbus point-to-point lines.

17. The apparatus of claim 11,

wherein the system controller comprises a first system controller;

wherein the apparatus further comprises a second system controller;

wherein the first system controller and second system controller are coupled to the first flash memory module and second flash memory module by a plurality of flashbus shared lines.

18. The apparatus of claim 13,

wherein flashbus point-to-point lines permit fault tolerant communications between the system controller and the plurality of flash memory modules.

19. A method comprising:

transmitting a memory transaction between a system controller and a first communication bus;

transmitting the memory transaction between the first communication bus and a flash bus interface;

transmitting the memory transaction between the flash bus interface and a second communication bus; and

transmitting the memory transaction between the second communication bus and a flash memory module.

20. The method of claim 19, wherein the system controller comprises a first system controller, said first system controller comprising:

a local bus interface;

an input/output device coupled to the local bus interface;

a processor coupled to the local bus interface; and

a memory module controller coupled to the local bus interface.