Health state of non-volatile memory

• US 9,875,812 B2
• Filed: 10/05/2015
• Issued: 01/23/2018
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Otterstedt, Jan, Schneckenburger, Christian
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): CHO, SUNG IL
• Application Number:
  US14/875,063
• Publication Number:
  US 20160125959A1
• Time in Patent Office: 841 Days
• Field of Search: 365201
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

An embodiment relates to a method for determining a health state of a non-volatile memory comprising: determining the health state based on at least one indicator for determining a predictable failure of the non-volatile memory.

Claims

1. A method for determining a health state of a non-volatile memory comprising:

iteratively stepwise adjusting a preceding signal amplitude applied in a corresponding preceding erase or write operation to determine a stepwise adjusted signal amplitude to be applied by a current erase or write operation until the current erase or write operation is successful;

determining a number of iterations of the stepwise adjustments;

determining an indicator based on the stepwise adjusted signal amplitude of the successful erase or write operation and the number of iterations of the stepwise adjustments; and

determining the health state based on the indicator to determine a predictable failure of the non-volatile memory.

2. The method according to claim 1, wherein the indicator is an indicator for an endurance failure, which is caused by erase operations and/or write operations.

3. The method according to claim 1, wherein the indicator is an indicator for a data retention failure.

4. The method according to claim 3, wherein the indicator for the data retention failure is determined based on an increased amount of read errors.

5. The method according to claim 3, wherein the indicator for the data retention failure is determined based on an increased amount of read errors that is determined under a hard read condition utilizing a hard read level.

6. The method according to claim 3, wherein the read errors are at least partially correctable by utilizing an error correction code.

7. The method according to claim 3, wherein the indicator for the data retention failure is determined based on an increased amount uncorrectable read errors.

8. The method according to claim 1, wherein the indicator is an indicator determined based on an decreasing amount of replacement units used for repair purposes.

9. The method according to claim 1, comprising

triggering a predefined action in case the health state wherein the health state fulfills a predefined condition.

10. The method according to claim 9, wherein the predefined action comprises a report or message.

11. The method according to claim 9, wherein the predefined condition may be based on the indicator and determine a statistical value to be compared with at least one threshold.

12. The method according to claim 1, wherein the non-volatile memory is at least one of the following:

an EEPROM;

a floating gate NVM;

a flash memory;

a PCRAM;

a RRAM;

a CBRAM;

a nano-crystal NVM;

a MONOS device;

a TANOS device; and

a MRAM.

13. A computer program product directly loadable into a memory of a digital processing device, comprising software code portions for performing the steps of the method according to claim 1.

14. The method according to claim 1, further comprising:

iteratively stepwise adjusting a duration of the preceding erase or write operation applied in the corresponding preceding erase or write operation to determine a stepwise adjusted signal duration to be applied by the current erase or write operation until the current erase or write operation is successful, wherein determining the indicator is further based on the stepwise adjusted signal duration of the successful erase or write operation.

15. The method according to claim 1, wherein determining the predictable failure of the non-volatile memory comprises determining a remaining lifetime of the non-volatile memory.

16. The method according to claim 15, wherein determining the remaining lifetime of the non-volatile memory comprises determining an estimated time period before the non-volatile memory suffers the predictable failure.

17. The method according to claim 16, wherein determining the remaining lifetime of the non-volatile memory further comprises determining an estimated number of successful erase or write operations that can be performed before the non-volatile memory suffers the predictable failure.

18. An integrated circuit comprising:

a non-volatile memory; and

circuitry configured to;

iteratively stepwise adjust a preceding signal amplitude applied in a corresponding preceding erase or write operation to determine a stepwise adjusted signal amplitude to be applied by a current erase or write operation until the current erase or write operation is successful;

determine a number of iterations of the stepwise adjustments;

determine an indicator based on the stepwise adjusted signal amplitude of the successful erase or write operation and the number of iterations of the stepwise adjustments; and

determine a health state of the non-volatile memory or a portion thereof based on the indicator to determine a predictable failure of the non-volatile memory.

19. The integrated circuit according to claim 18, wherein the integrated circuit is a microcontroller, a microprocessor or an ASIC.

20. A system comprising:

at least one integrated circuit comprising a non-volatile memory; and

a processor that is configured to;

iteratively stepwise adjust a preceding signal amplitude applied in a corresponding preceding erase or write operation to determine a stepwise adjusted signal amplitude to be applied by a current erase or write operation until the current erase or write operation is successful;

determine an indicator based on the stepwise adjusted signal amplitude of the successful erase or write operation and the number of iterations of the stepwise adjustments; and

determine a health state of the non-volatile memory or a portion thereof based on the indicator to determine a predictable failure of the non-volatile memory.