Preventive measures for adaptive flash tuning

• US 9,875,813 B2
• Filed: 06/27/2016
• Issued: 01/23/2018
• Est. Priority Date: 08/04/2014
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Nvmdurance Limited
• Inventors: Ryan, Conor Maurice, Sullivan, Joseph
• Primary Examiner(s): Beugh, Brian
• Application Number:
  US15/194,447
• Publication Number:
  US 20170133107A1
• Time in Patent Office: 575 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 : Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 : Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/36 : Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/38 : Response verification devices
• CPC Class Codes: G11C 29/44 : Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50012 : of timing
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).

Claims

1. A flash memory controller that controls the operation of one or more flash memory chips, each chip including one or more LUNs, and each LUN including one or more blocks of flash memory and one or more control registers storing operating parameters associated with that LUN, the flash memory controller comprising:

(a) a health metric interrupt module that;

(i) monitors a plurality of wear indicators that evidence degradation of the flash memory over time, wherein one of the plurality of wear indicators is a current cumulative number of program/erase cycles performed by the flash memory controller during the operational lifetime of the one or more flash memory chips,

(ii) generates a plurality of health metrics by analyzing and quantifying the plurality of wear indicators over time,

(iii) detects a plurality of threshold violations, wherein a threshold violation occurs when a function of a subset of the plurality of health metrics exceeds a predefined threshold, and

(iv) issues a threshold violation interrupt upon detection of a threshold violation, and includes, with the threshold violation interrupt, health metric data pertaining to the associated threshold violation;

and

(b) an inference engine that, in response to each threshold violation interrupt,

(i) generates one or more conditions based upon an analysis of (1) the health metric data pertaining to the associated threshold violation, and (2) historical health metric data pertaining to previous threshold violations, and

(ii) employs one or more preventive measures, based upon the conditions generated over time in response to threshold violation interrupts, to reduce the rate of degradation of the flash memory over time, and thereby extend the operational lifetime of the one or more flash memory chips.

2. The flash memory controller of claim 1, wherein the plurality of wear indicators includes BER data resulting from the flash memory controller reading the contents of the flash memory.

3. The flash memory controller of claim 1, wherein the plurality of wear indicators includes timing information with respect to read, write or erase commands issued by the flash memory controller.

4. The flash memory controller of claim 1, wherein the threshold violations are categorized into a plurality of types, including a critical and a non-critical type.

5. The flash memory controller of claim 1, wherein the historical health metric data include cumulative counts over time of threshold violations in individual LUNs of the one or more flash memory chips.

6. The flash memory controller of claim 1, wherein the historical health metric data include cumulative counts over time of threshold violations in individual blocks of a LUN of the one or more flash memory chips.

7. The flash memory controller of claim 1, wherein the preventive measures include resting one or more of the blocks of a LUN of the one or more flash memory chips.

8. The flash memory controller of claim 1, wherein the preventive measures include reducing the usage of one or more blocks of a LUN of the one or more flash memory chips.

9. The flash memory controller of claim 1, wherein the preventive measures include moving the data contents of a suspect block to another block in the one or more flash memory chips.

10. The flash memory controller of claim 1, wherein the preventive measures include modifying one or more of the predefined thresholds.

11. A method for controlling the operation of one or more flash memory chips, each chip including one or more LUNs, and each LUN including one or more blocks of flash memory and one or more control registers storing operating parameters associated with that LUN, the method comprising the following steps:

(a) monitoring a plurality of wear indicators that evidence degradation of the flash memory over time, wherein one of the plurality of wear indicators is a current cumulative number of program/erase cycles performed during the operational lifetime of the one or more flash memory chips;

(b) generating a plurality of health metrics by analyzing and quantifying the plurality of wear indicators over time;

(c) detecting a plurality of threshold violations, wherein a threshold violation occurs when a function of a subset of the plurality of health metrics exceeds a predefined threshold;

(d) issuing a threshold violation interrupt upon detection of a threshold violation, and including, with the threshold violation interrupt, health metric data pertaining to the associated threshold violation; and

(e) in response to each threshold violation interrupt;

(i) generating one or more conditions based upon an analysis of (1) the health metric data pertaining to the associated threshold violation, and (2) historical health metric data pertaining to previous threshold violations, and

(ii) employing one or more preventive measures, based upon the conditions generated over time in response to threshold violation interrupts, to reduce the rate of degradation of the flash memory over time, and thereby extend the operational lifetime of the one or more flash memory chips.

12. The method of claim 11, wherein the plurality of wear indicators includes BER data resulting from reading the contents of the flash memory.

13. The method of claim 11, wherein the plurality of wear indicators includes timing information with respect to read, write or erase commands.

14. The method of claim 11, wherein the threshold violations are categorized into a plurality of types, including a critical and a non-critical type.

15. The method of claim 11, wherein the historical health metric data include cumulative counts over time of threshold violations in individual LUNs of the one or more flash memory chips.

16. The method of claim 11, wherein the historical health metric data include cumulative counts over time of threshold violations in individual blocks of a LUN of the one or more flash memory chips.

17. The method of claim 11, wherein the preventive measures include resting one or more of the blocks of a LUN of the one or more flash memory chips.

18. The method of claim 11, wherein the preventive measures include reducing the usage of one or more blocks of a LUN of the one or more flash memory chips.

19. The method of claim 11, wherein the preventive measures include moving the data contents of a suspect block to another block in the one or more flash memory chips.

20. The method of claim 11, wherein the preventive measures include modifying one or more of the predefined thresholds.

21. A flash memory controller that controls the operation of one or more flash memory chips, each chip including one or more LUNs, and each LUN including one or more blocks of flash memory and one or more control registers storing operating parameters associated with that LUN, the flash memory controller comprising:

(a) an operating parameter database that stores, with respect to each LUN of the one or more flash memory chips, a plurality of sets of operating parameters, each set of operating parameters corresponding to a health stage representing an estimated level of degradation of the flash memory within that LUN;

(b) a health metric interrupt module that;

(i) monitors a plurality of wear indicators that evidence degradation of the flash memory over time, wherein one of the plurality of wear indicators is a current cumulative number of program/erase cycles performed by the flash memory controller during the operational lifetime of the one or more flash memory chips,

(ii) generates a plurality of health metrics by analyzing and quantifying the plurality of wear indicators over time,

(iii) detects a plurality of threshold violations, wherein a threshold violation occurs when a function of a subset of the plurality of health metrics exceeds a predefined threshold, and

(iv) issues a threshold violation interrupt upon detection of a threshold violation, and includes, with the threshold violation interrupt, health metric data pertaining to the associated threshold violation;

and

(c) an inference engine that, in response to each threshold violation interrupt,

(i) generates one or more conditions based upon an analysis of (1) the health metric data pertaining to the associated threshold violation, and (2) historical health metric data pertaining to previous threshold violations,

(ii) determines whether the conditions generated over time in response to threshold violation interrupts warrant transitioning a LUN from a current health stage to a subsequent health stage,

(iii) if the conditions do warrant transitioning the LUN to a subsequent health stage, replaces the contents of the LUN'"'"'s control registers with the set of operating parameters corresponding to the subsequent health stage, and

(iv) if the conditions do not warrant transitioning the LUN to a subsequent health stage, employs one or more less extreme preventive measures to reduce the rate of degradation of the flash memory over time during the current health stage, and thereby extend the operational lifetime of the one or more flash memory chips.

22. The flash memory controller of claim 21, wherein the plurality of wear indicators includes BER data resulting from the flash memory controller reading the contents of the flash memory.

23. The flash memory controller of claim 21, wherein the plurality of wear indicators includes timing information with respect to read, write or erase commands issued by the flash memory controller.

24. The flash memory controller of claim 21, wherein the threshold violations are categorized into a plurality of types, including a critical and a non-critical type.

25. The flash memory controller of claim 21, wherein the historical health metric data include cumulative counts over time of threshold violations in individual LUNs of the one or more flash memory chips.

26. The flash memory controller of claim 21, wherein the historical health metric data include cumulative counts over time of threshold violations in individual blocks of a LUN of the one or more flash memory chips.

27. The flash memory controller of claim 21, wherein the preventive measures include resting one or more of the blocks of a LUN of the one or more flash memory chips.

28. The flash memory controller of claim 21, wherein the preventive measures include reducing the usage of one or more blocks of a LUN of the one or more flash memory chips.

29. The flash memory controller of claim 21, wherein the preventive measures include moving the data contents of a suspect block to another block in the one or more flash memory chips.

30. The flash memory controller of claim 21, wherein the preventive measures include modifying one or more of the predefined thresholds.

31. The flash memory controller of claim 21, wherein, with respect to each health stage, the set of operating parameters corresponding to that health stage is the same for each LUN of each of the one or more flash memory chips.

32. The flash memory controller of claim 21, wherein the sets of operating parameters corresponding to the health stages are predetermined in an offline characterization phase prior to the operational lifetime of the one or more flash memory chips.

33. A method for controlling the operation of one or more flash memory chips, each chip including one or more LUNs, and each LUN including one or more blocks of flash memory and one or more control registers storing operating parameters associated with that LUN, the method comprising the following steps:

(a) storing, with respect to each LUN of the one or more flash memory chips, a plurality of sets of operating parameters, each set of operating parameters corresponding to a health stage representing an estimated level of degradation of the flash memory within that LUN;

(b) monitoring a plurality of wear indicators that evidence degradation of the flash memory over time, wherein one of the plurality of wear indicators is a current cumulative number of program/erase cycles performed during the operational lifetime of the one or more flash memory chips;

(c) generating a plurality of health metrics by analyzing and quantifying the plurality of wear indicators over time;

(d) detecting a plurality of threshold violations, wherein a threshold violation occurs when a function of a subset of the plurality of health metrics exceeds a predefined threshold;

(e) issuing a threshold violation interrupt upon detection of a threshold violation, and including, with the threshold violation interrupt, health metric data pertaining to the associated threshold violation; and

(f) in response to each threshold violation interrupt,

(i) generating one or more conditions based upon an analysis of (1) the health metric data pertaining to the associated threshold violation, and (2) historical health metric data pertaining to previous threshold violations,

(ii) determining whether the conditions generated over time in response to threshold violation interrupts warrant transitioning a LUN from a current health stage to a subsequent health stage,

(iii) if the conditions do warrant transitioning the LUN to a subsequent health stage, replacing the contents of the LUN'"'"'s control registers with the set of operating parameters corresponding to the subsequent health stage, and

(iv) if the conditions do not warrant transitioning the LUN to a subsequent health stage, employing one or more less extreme preventive measures to reduce the rate of degradation of the flash memory over time during the current health stage, and thereby extend the operational lifetime of the one or more flash memory chips.

34. The method of claim 33, wherein the plurality of wear indicators includes BER data resulting from reading the contents of the flash memory.

35. The method of claim 33, wherein the plurality of wear indicators includes timing information with respect to read, write or erase commands.

36. The method of claim 33, wherein the threshold violations are categorized into a plurality of types, including a critical and a non-critical type.

37. The method of claim 33, wherein the historical health metric data include cumulative counts over time of threshold violations in individual LUNs of the one or more flash memory chips.

38. The method of claim 33, wherein the historical health metric data include cumulative counts over time of threshold violations in individual blocks of a LUN of the one or more flash memory chips.

39. The method of claim 33, wherein the preventive measures include resting one or more of the blocks of a LUN of the one or more flash memory chips.

40. The method of claim 33, wherein the preventive measures include reducing the usage of one or more blocks of a LUN of the one or more flash memory chips.

41. The method of claim 33, wherein the preventive measures include moving the data contents of a suspect block to another block in the one or more flash memory chips.

42. The method of claim 33, wherein the preventive measures include modifying one or more of the predefined thresholds.

43. The method of claim 33, wherein, with respect to each health stage, the set of operating parameters corresponding to that health stage is the same for each LUN of each of the one or more flash memory chips.

44. The method of claim 33, wherein the sets of operating parameters corresponding to the health stages are predetermined in an offline characterization phase prior to the operational lifetime of the one or more flash memory chips.