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Configurations and methods for manufacturing charged balanced devices

  • US 9,876,072 B2
  • Filed: 06/14/2016
  • Issued: 01/23/2018
  • Est. Priority Date: 01/08/2006
  • Status: Active Grant
First Claim
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1. A semiconductor power device supported in a uniformly doped substrate of a first conductivity type;

  • wherein the semiconductor power comprising;

    deep trenches etched into the uniformly doped substrate wherein the uniformly doped substrate lateral to the deep trenches constituting a drift region for the semiconductor power device;

    an epitaxial layer of a second conductivity type filling the deep trenches to charge balance the drift region, wherein the epitaxial layer filling the deep trenches and forming a top thin epitaxial layer over the top surface of the semiconductor substrate;

    a highly doped drain region of the first conductivity type disposed at the bottom of the semiconductor substrate wherein the drain region contacts a drain metal electrode disposed at a backside of the semiconductor substrate below the drain region;

    a plurality of trench MOSFET cells each having a trenched gate opened from the top epitaxial layer of the second conductivity type filled with a gate material and extends into the semiconductor regions between the deep trenches with the top epitaxial layer of the second conductivity type functioning as the body region encompassing doped regions of the first conductivity type functioning as source regions andeach of the trench MOSFET cells having shallow trench gate sidewall dopant regions surrounding sidewalls of the trenched gate and a gate-bottom dopant region below the trenched gate, wherein the gate sidewall dopant regions and gate-bottom dopant regions are of the first conductivity type.

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