Semiconductor structure with stress-reducing buffer structure
First Claim
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1. A semiconductor structure comprising:
- a buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands formed of a first semiconductor material and laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer of the first semiconductor material, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and
a set of semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa.
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Abstract
A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
23 Citations
20 Claims
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1. A semiconductor structure comprising:
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a buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands formed of a first semiconductor material and laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer of the first semiconductor material, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and a set of semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An optoelectronic device comprising:
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a buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands formed of a first semiconductor material and laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer of the first semiconductor material, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and a set of semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include; an n-type layer located on the buffer structure; an active region located on a side of the n-type layer opposite the buffer structure; and a p-type layer located on a side of the active region opposite the n-type layer. - View Dependent Claims (16, 17)
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18. An optoelectronic device comprising:
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a nitride-based buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands formed of a first nitride-based material and laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer of the first nitride-based material, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and a set of group III nitride-based semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa, wherein the set of semiconductor layers include; a group III nitride-based n-type layer located on the buffer structure; a group III nitride-based active region located on a side of the n-type layer opposite the buffer structure, wherein the active region is configured to emit ultraviolet radiation; and a group III nitride-based p-type layer located on a side of the active region opposite the n-type layer. - View Dependent Claims (19, 20)
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Specification