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Semiconductor structure with stress-reducing buffer structure

  • US 9,876,140 B2
  • Filed: 08/08/2016
  • Issued: 01/23/2018
  • Est. Priority Date: 02/22/2014
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • a buffer structure including a buffer layer, wherein the buffer layer has a first side including a plurality of islands formed of a first semiconductor material and laterally separated from any other semiconductor material and a second side opposite the first side at which the islands are coalesced into a single layer of the first semiconductor material, wherein the coalesced portion of the buffer layer has a thickness in a range of approximately 100 Angstroms to approximately 100 microns; and

    a set of semiconductor layers formed adjacent to the second side of the buffer structure, wherein the buffer structure has an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa.

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