Semiconductor device
First Claim
Patent Images
1. A semiconductor device comprising:
- a NAND decoder including six transistors, each having a source, a drain, and a gate layered in a direction perpendicular to a substrate, the six transistors on the substrate in a line extending in a first direction,each of the six transistors includinga silicon pillar,an insulator surrounding a side surface of the silicon pillar,a gate surrounding the insulator,a source region in an upper portion or a lower portion of the silicon pillar, anda drain region in the upper portion or the lower portion of the silicon pillar, the drain region located on a side of the silicon pillar opposite to the source region,the six transistors comprising;
a first p-channel MOS transistor,a second p-channel MOS transistor,a third p-channel MOS transistor,a first n-channel MOS transistor,a second n-channel MOS transistor, anda third n-channel MOS transistor,the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line,the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line,the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line,the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, respectively, and connected to one another at an output terminal,the source region of the second n-channel MOS transistor and the drain region of the third n-channel MOS transistor located closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor,the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor,the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor,the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line,the source region of the third n-channel MOS transistor connected to a reference power supply line,the NAND decoder further includinga first address signal line,a second address signal line, anda third address signal line,the first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor connected to the first address signal line,the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to the second address signal line,the third gate line of the third p-channel MOS transistor and the third n-channel MOS transistor connected to the third address signal line,the first, second, and third gate lines extending the first direction, andthe power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line in a second direction perpendicular to the first direction.
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Accused Products
Abstract
A semiconductor device includes a 3-input NAND decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.
4 Citations
36 Claims
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1. A semiconductor device comprising:
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a NAND decoder including six transistors, each having a source, a drain, and a gate layered in a direction perpendicular to a substrate, the six transistors on the substrate in a line extending in a first direction, each of the six transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region located on a side of the silicon pillar opposite to the source region, the six transistors comprising; a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, and a third n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, respectively, and connected to one another at an output terminal, the source region of the second n-channel MOS transistor and the drain region of the third n-channel MOS transistor located closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line, the source region of the third n-channel MOS transistor connected to a reference power supply line, the NAND decoder further including a first address signal line, a second address signal line, and a third address signal line, the first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor connected to the first address signal line, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to the second address signal line, the third gate line of the third p-channel MOS transistor and the third n-channel MOS transistor connected to the third address signal line, the first, second, and third gate lines extending the first direction, and the power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line in a second direction perpendicular to the first direction. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising:
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a number of first address signal lines (a); a number of second address signal lines (b); a number of third address signal lines (c) and a×
b×
c NAND decoders,each of the a×
b×
c NAND decoders including six transistors, each having a source, a drain, and a gate layered in a direction perpendicular to a substrate, the six transistors on the substrate in a line extending in a first direction,each of the six transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region located on a side of the silicon pillar opposite to the source region, the six transistors at least including a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, and a third n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, respectively, and connected to one another at an output terminal, the source region of the second n-channel MOS transistor and the drain region of the third n-channel MOS transistor located closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor being connected to a power supply line, the source region of the third n-channel MOS transistor connected to a reference power supply line, each of the a×
b×
c NAND decoders configured such thatthe first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor connected to any one of the a first address signal lines, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to any one of the second address signal lines, and the third gate line of the third p-channel MOS transistor and the third n-channel MOS transistor connected to any one of the third address signal lines, the first, second, and third gate lines extending in the first direction, and the power supply line, the reference power supply line, the first address signal lines, the second address signal lines, and the third address signal lines extending in a second direction perpendicular to the first direction. - View Dependent Claims (6, 7, 8)
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9. A semiconductor device comprising:
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a NAND decoder including six transistors, each having a source, a drain, and a gate layered in a direction perpendicular to a substrate, the six transistors on the substrate in a line extending in a first direction, each of the six transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region located on a side of the silicon pillar opposite to the source region, the six transistors comprising; a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, and a third n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, the drain region of the second n-channel MOS transistor and the source region of the third n-channel MOS transistor located closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor connected to one another at an output terminal, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source region of the third n-channel MOS transistor connected to a reference power supply line, the NAND decoder further including a first address signal line, a second address signal line, and a third address signal line, the first gate of the first p-channel MOS transistor and the first n-channel MOS transistor connected to the first address signal line, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to the second address signal line, the third gate line of the third p-channel MOS transistor and the third n-channel MOS transistor connected to the third address signal line, the first, second, and third gate lines extending in the first direction, and the power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extending in a second direction perpendicular to the first direction. - View Dependent Claims (10, 11, 12)
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13. A semiconductor device comprising:
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first address signal lines (a); second address signal lines (b); third address signal lines (c); and a×
b×
c NAND decoders,each of the a×
b×
c NAND decoders including six transistors, each having a source, a drain, and a gate layered manner in a direction perpendicular to a substrate, the six transistors on the substrate in a line in a first direction,each of the six transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region on a side of the silicon pillar opposite to the source region, the six transistors at least including a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, and a third n-channel MOS transistor, the gate of the first p-channel MOS transistor and the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, the drain region of the second n-channel MOS transistor and the source region of the third n-channel MOS transistor closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor connected to one another at an output terminal, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source region of the third n-channel MOS transistor connected to a reference power supply line, each of the a×
b×
c NAND decoders configured such thatthe first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor, connected to any one of the first address signal lines, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to any one of the second address signal lines, and the third gate line of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to any one of the third address signal lines, the first, second, and third gate lines extending in the first direction, and the power supply line, the reference power supply line, the first address signal lines, the second address signal lines, and the third address signal lines extending in a second direction perpendicular to the first direction. - View Dependent Claims (14, 15, 16, 17)
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18. A semiconductor device comprising:
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a NAND decoder; and an inverter, the NAND decoder and the inverter including eight transistors, each having a source, a drain, and a gate layered in a direction perpendicular to a substrate, the eight transistors on the substrate in a line extending in a first direction, each of the eight transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region on a side of the silicon pillar opposite to the source region, the eight transistors including a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a fourth p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, a third n-channel MOS transistor, and a fourth n-channel MOS transistor, the NAND decoder including the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor, and the third n-channel MOS transistor, the inverter including the fourth p-channel MOS transistor, and the fourth n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, respectively, and connected to one another at a first output terminal, the source region of the second n-channel MOS transistor and the drain region of the third n-channel MOS transistor closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source region of the third n-channel MOS transistor connected to a reference power supply line, the gate of the fourth p-channel MOS transistor and the gate of the fourth n-channel MOS transistor connected to the first output terminal, the drain region of the fourth p-channel MOS transistor and the drain region of the fourth n-channel MOS transistor connected at a second output terminal, the source region of the fourth p-channel MOS transistor and the source region of the fourth n-channel MOS transistor respectively connected to the power supply line and the reference power supply line, the NAND decoder further including a first address signal line, a second address signal line, and a third address signal line, the first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor connected to the first address signal line, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to the second address signal line, the third gate of the third p-channel MOS transistor and the third n-channel MOS transistor connected to the third address signal line, the first, second, and third gate lines extending in the first direction, and the power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extending in a second direction perpendicular to the first direction. - View Dependent Claims (19, 20, 21)
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22. A semiconductor device comprising:
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first address signal lines (a); second address signal lines (b); third address signal lines (c); and a×
b×
c pairs of NAND decoders and inverters,each of the a×
b×
c pairs of NAND decoders and inverters including eight transistors, each having a source, a drain, and a gate layered in a direction perpendicular to a substrate, the eight transistors on the substrate in a line extending in a first direction,each of the eight transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region on a side of the silicon pillar opposite to the source region, the eight transistors including a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a fourth p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, a third n-channel MOS transistor, and a fourth n-channel MOS transistor, the decoder at least including the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor, and the third n-channel MOS transistor, the inverter including the fourth p-channel MOS transistor, and the fourth n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, respectively, and jointly connected at a first output terminal, the source region of the second n-channel MOS transistor and the drain region of the third n-channel MOS transistor closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source region of the third n-channel MOS transistor connected to a reference power supply line, the gate of the fourth p-channel MOS transistor and the gate of the fourth n-channel MOS transistor jointly connected at the first output terminal, the drain region of the fourth p-channel MOS transistor and the drain region of the fourth n-channel MOS transistor jointly connected at a second output terminal, the source region of the fourth p-channel MOS transistor and the source region of the fourth n-channel MOS transistor being respectively connected to the power supply line and the reference power supply line, each of the a×
b×
c pairs of NAND decoders and inverters configured such thatthe first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor connected to any one of the first address signal lines, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to any one of the second address signal lines, and the third gate line of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to any one of the third address signal lines, the first, second, and third gate lines extending in the first direction, and the power supply line, the reference power supply line, the first address signal lines, the second address signal lines, and the third address signal lines extending in a second direction perpendicular to the first direction. - View Dependent Claims (23, 24, 25)
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26. A semiconductor device comprising:
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a NAND decoder; and an inverter, the NAND decoder and the inverter including eight transistors, each having a source, a drain, and a gate layered in a direction perpendicular to a substrate, the eight transistors on the substrate in a line extending in a first direction, each of the eight transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region disposed in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region located on a side of the silicon pillar opposite to the source region, the eight transistors including a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a fourth p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, a third n-channel MOS transistor, and a fourth n-channel MOS transistor, the NAND decoder including the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor, and the third n-channel MOS transistor, the inverter including the fourth p-channel MOS transistor, and the fourth n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor being closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, the drain region of the second n-channel MOS transistor and the source region of the third n-channel MOS transistor located closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor jointly connected at a first output terminal, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source region of the third n-channel MOS transistor connected to a reference power supply line, the gate of the fourth p-channel MOS transistor and the gate of the fourth n-channel MOS transistor jointly connected to the first output terminal, the drain region of the fourth p-channel MOS transistor and the drain region of the fourth n-channel MOS transistor jointly connected at a second output terminal, the source region of the fourth p-channel MOS transistor and the source region of the fourth n-channel MOS transistor respectively connected to the power supply line and the reference power supply line, the NAND decoder further including a first address signal line, a second address signal line, and a third address signal line, the first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor connected to the first address signal line, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to the second address signal line, the third gate line of the third p-channel MOS transistor and the third n-channel MOS transistor connected to the third address signal line, the first, second, and third gate lines extending in the first direction, and the power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extending in a second direction perpendicular to the first direction. - View Dependent Claims (27, 28, 29, 30)
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31. A semiconductor device comprising:
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first address signal lines (a); second address signal lines (b); third address signal lines (c); and a×
b×
c pairs of NAND decoders and inverters,each of the a×
b×
c pairs of NAND decoders and inverters including eight transistors, each having a source, a drain, and a gate arranged in a layered manner in a direction perpendicular to a substrate, the eight transistors on the substrate in a line extending in a first direction,each of the eight transistors including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region in an upper portion or a lower portion of the silicon pillar, and a drain region in the upper portion or the lower portion of the silicon pillar, the drain region on a side of the silicon pillar opposite to the source region, the eight transistors including a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor, a fourth p-channel MOS transistor, a first n-channel MOS transistor, a second n-channel MOS transistor, a third n-channel MOS transistor, and a fourth n-channel MOS transistor, each of the a×
b×
c NAND decoders includingthe first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, the first n-channel MOS transistor, the second n-channel MOS transistor, and the third n-channel MOS transistor, each of the a×
b×
c inverters includingthe fourth p-channel MOS transistor, and the fourth n-channel MOS transistor, the gate of the first p-channel MOS transistor and the gate of the first n-channel MOS transistor connected to each other by a first gate line, the gate of the second p-channel MOS transistor and the gate of the second n-channel MOS transistor connected to each other by a second gate line, the gate of the third p-channel MOS transistor and the gate of the third n-channel MOS transistor connected to each other by a third gate line, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor located closer to the substrate than the silicon pillars of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor, the drain region of the second n-channel MOS transistor and the source region of the third n-channel MOS transistor located closer to the substrate than the silicon pillars of the second n-channel MOS transistor and the third n-channel MOS transistor, the drain regions of the first p-channel MOS transistor, the second p-channel MOS transistor, the third p-channel MOS transistor, and the first n-channel MOS transistor jointly connected at a first output terminal, the source regions of the first p-channel MOS transistor, the second p-channel MOS transistor, and the third p-channel MOS transistor connected to a power supply line, the source region of the first n-channel MOS transistor connected to the drain region of the second n-channel MOS transistor, the source region of the second n-channel MOS transistor connected to the drain region of the third n-channel MOS transistor, the source region of the third n-channel MOS transistor connected to a reference power supply line, the gate of the fourth p-channel MOS transistor and the gate of the fourth n-channel MOS transistor jointly connected to the first output terminal, the drain region of the fourth p-channel MOS transistor and the drain region of the fourth n-channel MOS transistor connected at a second output terminal, the source region of the fourth p-channel MOS transistor and the source region of the fourth n-channel MOS transistor respectively connected to the power supply line and the reference power supply line, each of the a×
b×
c pairs of NAND decoders and inverters configured such that,the first gate line of the first p-channel MOS transistor and the first n-channel MOS transistor connected to any one of the a first address signal lines, the second gate line of the second p-channel MOS transistor and the second n-channel MOS transistor connected to any one of the second address signal lines, and the third gate line of the third p-channel MOS transistor and the third n-channel MOS transistor connected to any one of the third address signal lines, the first, second, and third gate lines extending in the first direction, and the power supply line, the reference power supply line, the first address signal lines, the second address signal lines, and the third address signal lines extending in a second direction perpendicular to the first direction. - View Dependent Claims (32, 33, 34, 35, 36)
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Specification
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Current AssigneeUnisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
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Original AssigneeUnisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
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InventorsMasuoka, Fujio, Asano, Masamichi
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Primary Examiner(s)Taningco, Alexander H
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Assistant Examiner(s)Kim, Seokjin
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Application NumberUS15/214,912Publication NumberTime in Patent Office552 DaysField of SearchUS Class CurrentCPC Class CodesH01L 21/823885 with a particular manufactu...H01L 21/84 the substrate being other t...H01L 23/528 Geometry or layout of the i...H01L 23/53209 based on metals, e.g. alloy...H01L 27/0207 Geometrical layout of the c...H01L 27/092 complementary MIS field-eff...H01L 27/1203 the substrate comprising an...H01L 29/78642 Vertical transistorsH03K 19/0948 using CMOS or complementary...H03K 19/20 characterised by logic func...
