System(s), method(s), and apparatus for accurate detection of the end of stream

• US 9,876,599 B2
• Filed: 12/17/2007
• Issued: 01/23/2018
• Est. Priority Date: 12/17/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Ross, Steven, Kumar, Vijay, Zhou, Jean
• Primary Examiner(s): Clawson, Stephen J
• Application Number:
  US11/958,272
• Publication Number:
  US 20090154502A1
• Time in Patent Office: 3,690 Days
• Field of Search: 370535, 370473, 370476
• CPC Class Codes: H04J 3/0602 Systems characterised by the synchronising information used
• CPC Class Codes: H04J 3/247 ATM or packet multiplexing
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00

Abstract

A multimedia presentation system for presenting multimedia data comprising a demultiplexing unit and at least one processing unit. The demultiplexing unit demultiplexes a plurality of streams of data. At least one presentation processing unit provides the plurality of stream of data for presentation according to predetermined timing and detecting an end of any one of the plurality of streams of data.

Claims

1. A circuit for presenting data, said circuit comprising:

interface circuitry configured to receive multiplexed packets from a media source, wherein said multiplexed packets carry a plurality of different individual synchronized streams of audio and video data multiplexed into a single multiplexed data stream;

controller circuitry configured to;

examine each of the multiplexed packets and detect an end of each of said plurality of synchronized streams of data in only some of the multiplexed packets forming the multiplexed data stream received by the interface circuitry; and

modify the multiplexed data stream to be a modified multiplexed data stream by selectively appending markers to each synchronized stream of data within the multiplexed data stream, said markers appended to only indicate those multiplexed packets that include a detected end of a respective synchronized stream of data for each of said plurality of synchronized streams of data within said modified multiplexed data stream;

demultiplexing circuitry configured to receive the modified multiplexed data stream and demultiplex the modified multiplexed data stream to generate demultiplexed streams of data; and

presentation processing circuitry comprising a first decoder circuitry configured to decode and output one of the demultiplexed streams of data of a first multimedia type for presentation, and a second decoder circuitry configured to decode and output the demultiplexed streams of data of a second multimedia type for presentation, the first decoder circuitry configured to signal the second decoder circuitry when each of the markers in the demultiplexed streams of data of the first multimedia type are detected.

2. The circuit of claim 1, wherein the interface circuitry writes the modified multiplexed data stream to a Random Access Memory (RAM).

3. The circuit of claim 1, wherein modification of the multiplexed data stream by selectively appending markers further comprises the marker being written by the controller circuitry in a header of a multiplexed packet identified from the multiplexed data stream as including a detected endpoint of a respective synchronized stream of data.

4. The circuit of claim 1, wherein modification of the multiplexed data stream by appending markers further comprises addition of an additional packet to the multiplexed data stream to form the modified multiplexed data stream, said additional packet indicative of an end of only one of the plurality of different synchronized streams of data included in the multiplexed data stream.

5. The circuit of claim 1, wherein one of the demultiplexed synchronized streams of data comprises an audio elementary stream and wherein the presentation processing circuitry comprises:

audio decoder circuitry configured to decode audio data for presentation, and detect the marker in the audio elementary stream.

6. The circuit of claim 5, wherein the audio decoder circuitry is configured to decode the audio data for presentation by decompressing the audio elementary stream.

7. The circuit of claim 5, wherein the one of the demultiplexed synchronized streams of data comprises a video elementary stream, and wherein the presentation processing circuitry comprises:

video processor circuitry configured to provide the video elementary stream for presentation, and detect the marker in the video elementary stream.

8. The circuit of claim 7, wherein the presentation processing circuitry further comprises:

video decoder circuitry configured to decompress the video elementary stream.

9. The circuit of claim 1, wherein the demultiplexed synchronized streams of data comprise a stream of graphics data, and wherein the presentation processing circuitry comprises:

graphics processor circuitry configured to provide graphics data for presentation, and detect the marker in the stream of graphics data.

10. The circuit of claim 9, wherein the presentation processing circuitry further comprises:

graphics decoder circuitry configured to decompress the stream of graphics data.

11. The circuit of claim 1, wherein the presentation processing circuitry is configured to detect the markers prior to playback of the synchronized streams of data.

12. The circuitry of claim 1, wherein the presentation processing circuitry further comprises an audio processing unit configured to output the demultiplexed synchronized streams of data that carry audio data and a video processing unit to output the demultiplexed synchronized streams of data that carry video data, the audio processing unit to notify the video processing unit when the markers in the synchronized streams of data that carry the audio data are detected and the video processing unit to notify the audio processing unit when the markers in the synchronized streams of data that carry the video data are detected.

13. A method for presenting data, said method comprising:

receiving, with interface circuitry, multiplexed packets from a media source, wherein said multiplexed packets carry a plurality of different individual streams of video and audio data multiplexed into a single multiplexed data stream;

examining, with interface circuitry, each of the multiplexed packets within the multiplexed stream for respective end points of each of said plurality of different individual streams included within the multiplexed data stream;

detecting, with the interface circuitry, respective end points of said plurality of different individual streams within some of the examined multiplexed packets of the multiplexed data stream received by the interface circuitry by identifying an end point of a respective data stream in a respective multiplexed packet;

modifying, with the interface circuitry, the multiplexed data stream by selectively appending markers to at least some of the different individual streams of data within the multiplexed data stream, said markers selectively appended to identify only the respective end points of each of said plurality of different individual streams of data;

receiving, with demultiplexer circuitry, the modified multiplexed data stream;

demultiplexing, with the demultiplexer circuitry, the modified multiplexed data stream to obtain demultiplexed different individual streams of data;

outputting, with presentation circuitry, the demultiplexed different individual streams of data for presentation according to a predetermined timing;

detecting, with the presentation circuitry, the marker for each of said demultiplexed different individual streams of data; and

outputting, with the presentation circuitry, a respective signal for each of the demultiplexed different individual streams of data in response to detection of the respective marker, the respective signal indicative of an end of a respective demultiplexed individual stream.

14. The method of claim 13, further comprising:

writing, with the interface circuitry, the modified multiplexed data stream to a Random Access Memory (RAM);

receiving from the RAM and demultiplexing the modified multiplexed data stream, with demultiplexer circuitry, to generate a plurality of demultiplexed streams of data; and

decoding and outputting, with decoder circuitry, each of the demultiplexed streams of data for presentation based on the respective markers.

15. The method of claim 13, wherein modifying the multiplexed data stream by appending further comprises writing the marker in a packet header of a respective multiplexed packet included in the multiplexed data stream in which a detected end of a respective synchronized stream of data is included.

16. The method of claim 13, wherein modifying the multiplexed data stream by appending markers further comprises adding an additional packet to the multiplexed data stream to form the modified multiplexed data stream, said additional packet indicating an end of only one of the plurality of different individual streams of data included in the multiplexed data stream.

17. The method of claim 13, wherein outputting the demultiplexed different individual streams of data further comprises:

decompressing an audio elementary stream included among the demultiplexed different individual streams of data.

18. The method of claim 13, wherein outputting the demultiplexed different individual streams of data further comprises:

decompressing a video elementary stream included among the demultiplexed different individual streams of data.

19. The method of claim 13, wherein outputting the demultiplexed different individual streams of data further comprises:

decompressing a graphics stream included among the demultiplexed different individual streams of data.

20. The method of claim 13, further comprising detecting the end points prior to playback of the different individual streams of data.

21. A device comprising:

a memory; and

at least one processor circuit configured to;

receive multiplexed packets from a media source, wherein said multiplexed packets carry a plurality of different individual synchronized streams of audio and video data multiplexed into a single multiplexed data stream;

examine each of the multiplexed packets and detect an end of each of said plurality of synchronized streams of data in only some of the multiplexed packets forming the multiplexed data stream;

modify the multiplexed data stream to be a modified multiplexed data stream by selectively appending markers to each synchronized stream of data within the multiplexed data stream, said markers appended to only indicate those multiplexed packets that include a detected end of a respective synchronized stream of data for each of said plurality of synchronized streams of data within said modified multiplexed data stream;

demultiplex the modified multiplexed synchronized streams of data to generate demultiplexed synchronized streams of data;

output, by an audio processing unit, the demultiplexed synchronized streams of data that carry audio data, and output, by a video processing unit, the demultiplexed synchronized streams of data that carry video data;

notify, by the audio processing unit, the video processing unit when the markers in the synchronized streams of data that carry the audio data are detected; and

notify, by the video processing unit, the audio processing unit when the markers in the synchronized streams of data that carry the video data are detected.

22. The device of claim 21, wherein the demultiplexed synchronized streams of data comprise a stream of graphics data, and the at least one processor circuit is further configured to:

provide graphics data for presentation, and detect the marker in the stream of graphics data.

23. The device of claim 22, wherein the at least one processor circuit is further configured to decompress the stream of graphics data.