Semiconductor device

• US 9,880,285 B2
• Filed: 11/11/2014
• Issued: 01/30/2018
• Est. Priority Date: 11/13/2013
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kitazawa, Takeo, Hatanaka, Koichi, Chiba, Shigeto
• Primary Examiner(s): Dang, Phuc
• Application Number:
  US14/538,235
• Publication Number:
  US 20150130662A1
• Time in Patent Office: 1,176 Days
• CPC Class Codes: G01S 19/35 Constructional details or hardware or software details of the signal processing chain
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 2224/14132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 28/10 Inductors

Abstract

A semiconductor device includes: a substrate; a first layer that is stacked on the substrate and includes an inductor; and a bump group that is arranged above the first layer, wherein the bump group includes a plurality of bumps that are arranged under a predetermined rule, and at least one bump that is different from the plurality of bumps and whose center does not overlap the inductor when the semiconductor device is viewed in a plan view from a direction vertical to a plane on which the bump group is provided.

Claims

1. A semiconductor device comprising:

a substrate;

a first layer that is stacked on the substrate and includes an inductor; and

a bump group that is arranged above the first layer, wherein

the bump group includes

a plurality of bumps that are arranged under a predetermined rule, and

at least one bump, wherein (i) the at least one bump is different from the plurality of bumps, (ii) at least a portion of the at least one bump overlaps the inductor when the semiconductor device is viewed in a plan view from a direction vertical to a plane on which the bump group is provided, and (iii) a center of the at least one bump does not overlap the inductor when the semiconductor device is viewed in the plan view.

2. An electronic apparatus comprising the semiconductor device according to claim 1.

3. A semiconductor device, comprising:

a substrate;

a first layer that is stacked on the substrate and includes an inductor; and

a bump group that is arranged above the first layer, wherein

the bump group includes

a plurality of bumps that are arranged under a predetermined rule, and

at least one bump that is different from the plurality of bumps and whose center does not overlap the inductor when the semiconductor device is viewed in a plan view from a direction vertical to a plane on which the bump group is provided, wherein

the substrate is a rectangle in shape in the plan view from the direction vertical to the plane on which the bump group is provided,

the inductor is located at any of corner portions of the rectangle in the plan view from the direction vertical to the plane on which the bump group is provided, and

the semiconductor device further includes

an analog signal processing circuit portion that includes the inductor and processes an analog signal to output a digital signal, and

a digital signal processing circuit portion that processes the digital signal and is provided spaced apart from the analog signal processing circuit portion in the plan view from the direction vertical to the plane on which the bump group is provided.

4. The semiconductor device according to claim 3, wherein

the analog signal processing circuit portion includes a power supply circuit portion between the inductor and the digital signal processing circuit portion in the plan view from the direction vertical to the plane on which the bump group is provided.

5. The semiconductor device according to claim 3, wherein

the digital signal processing circuit portion includes

a first memory that operates at a first operating frequency, and

a second memory that operates at a second operating frequency lower than the first operating frequency, and

a distance between the first memory and the analog signal processing circuit portion is longer than a distance between the second memory and the analog signal processing circuit portion.

6. The semiconductor device according to claim 3, wherein

the analog signal processing circuit portion is a receiver circuit portion that receives an analog signal.

7. The semiconductor device according to claim 6 further comprising an LNA (Low Noise Amplifier), wherein

the LNA includes the inductor.

8. The semiconductor device according to claim 6, wherein

the analog signal is a positioning satellite signal,

the digital signal processing circuit portion includes

a correlation operation circuit portion that performs a correlation operation for capturing the positioning satellite signal, and

a first memory that operates at a first operating frequency, and

a distance between the first memory and the analog signal processing circuit portion is longer than a distance between the correlation operation circuit portion and the analog signal processing circuit portion.

9. The semiconductor device according to claim 3, wherein

the analog signal processing circuit portion includes three or more the inductors, and the area of a polygon obtained by connecting centers of the respective inductors in the plan view is from 0.08 mm2 to 0.116 mm2.