Low power autonomous peripheral management

• US 9,880,583 B2
• Filed: 10/20/2015
• Issued: 01/30/2018
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: Ambiq Micro, Inc.
• Original Assignee: Ambiq Micro, Inc.
• Inventors: Sheafor, Stephen James, Hanson, Scott, Popps, Donovan
• Primary Examiner(s): Abad, Farley
• Application Number:
  US14/918,397
• Publication Number:
  US 20160110299A1
• Time in Patent Office: 833 Days
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3041 where the computing system component is an input/output interface interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00
• CPC Class Codes: G06F 11/3414 Workload generation, e.g. scripts, playback
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

Claims

1. An autonomous peripheral facility comprising:

a central processing unit (CPU) adapted to develop a first input;

a peripheral device adapted to receive a first data input, develop a first data output, and develop a first information data; and

a peripheral controller comprising a configuration register, a state machine, a control unit, and a memory, said peripheral controller being adapted to receive said first input, to exchange said first information data, and to autonomously operate said peripheral device, independent of said CPU after receiving said first input;

wherein;

said configuration register is further adapted to receive said first input and develop a first control data as a function of said first input;

said peripheral device is further adapted to exchange said first information data with a selected one of said control unit and said memory;

said state machine is further adapted to;

selectively receive a trigger;

selectively sequence a plurality of peripheral modes as a function of said first control data and said trigger;

selectively develop a first completion signal as a function of said first control data; and

selectively develop a first power switch signal as a function of said first control data;

said control unit is further adapted to;

exchange said first information data with said peripheral device, said memory, and said state machine;

selectively sequence a plurality of peripheral power states as a function of said first control data and said trigger; and

selectively develop a plurality of clocks as a function of said first control data and said trigger; and

said memory adapted to store said first information data.

2. The autonomous peripheral facility of claim 1 wherein said trigger is further characterized as being a function of said first control data.