Memory appliance for accessing memory

• US 9,880,971 B2
• Filed: 11/12/2014
• Issued: 01/30/2018
• Est. Priority Date: 12/20/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Lowery, Keith, Fruchter, Vlad, Yeung, Chi-Ming
• Primary Examiner(s): Rossiter, Sean D
• Application Number:
  US14/539,641
• Publication Number:
  US 20150178002A1
• Time in Patent Office: 1,175 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G06F 12/0692 Multiconfiguration, e.g. local and global addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/568 Storing data temporarily at an intermediate stage, e.g. caching

Abstract

A memory appliance system is described and includes a processor coupled to one or more communication channels with a command interface, wherein the processor is configured for communicating commands over the communication channels. A plurality of Smart Memory Cubes (SMCs) is coupled to the processor through the communication channels. Each of the SMCs includes a controller that is programmable, and a plurality of memory devices. The controller is configured to respond to commands from the command interface to access content stored in one or more of the plurality of memory devices and to perform data operations on content accessed from the plurality of memory devices.

Claims

1. A memory appliance system comprising:

a processor operable to be coupled to one or more communication channels with a command interface, said processor for communicating a command over said one or more communication channels; and

a plurality of smart memory cubes (SMCs) coupled to said processor through said one or more communication channels, wherein each SMC comprises;

a controller that is programmable; and

a plurality of memory devices, wherein said controller is configured to respond to said command from said command interface by performing a plurality of data operations comprising a read operation and a write operation on content stored in one or more of said plurality of memory devices.

2. The memory appliance system of claim 1, where said processor comprises a host controller and is configured to provide services comprising load balancing, quality of service, connection management, or traffic routing services.

3. The memory appliance system of claim 1, wherein said controller in a corresponding SMC comprises a field programmable gate array.

4. The memory appliance system of claim 1, wherein said plurality of memory devices comprise memory devices packaged in a dual in-line memory module (DIMM).

5. The memory appliance system of claim 1, wherein a communication channel comprises one of transmission control protocol (TCP);

user datagram protocol (UDP);

Ethernet; and

Infiniband.

6. The memory appliance system of claim 1, wherein said communication channel comprises a direct interface comprising a peripheral component interconnect express (PCIe) interface.

7. The memory appliance system of claim 1, wherein said plurality of memory devices comprises a memcached memory system accessed through a plurality of memcached key value functions.

8. A memory appliance system comprising:

a processor operable to be coupled to one or more communication channels with a command interface, said processor for communicating a command over said one or more communication channels; and

a plurality of memory units coupled to said processor through said one or more communication channels, wherein each memory unit comprises;

a plurality of memory devices; and

a controller configured to be programmed to perform one of multiple functions based on a configuration indication;

wherein said controller is configured to respond to said command from said command interface by performing a plurality of data operations comprising a read operation and a write operation based on the configuration indication and to perform said plurality of data operations on content of said plurality of memory devices.

9. The memory appliance system of claim 8, wherein the configuration indication is one configuration file of a library of multiple configuration files.

10. The memory appliance system of claim 9, wherein said controller is configured by a configuration file to be programmed to perform a search operation.

11. The memory appliance system of claim 9, wherein said controller is configured by a configuration file to be programmed to perform a sort operation.

12. The memory appliance system of claim 9, wherein said controller is configured by a configuration file to be programmed to perform a custom acceleration operation.

13. The memory appliance system of claim 8, wherein said controller in a corresponding SMC comprises a field programmable gate array.

14. The memory appliance system of claim 8, wherein said plurality of memory devices comprise memory devices packaged in a dual in-line memory module (DIMM), registered DIMM (RDIMM), or load reduced DIMM (LRDIMM).

15. A memory appliance system comprising:

a processor operable to be coupled to one or more communication channels with a command interface, said processor for communicating a command over said one or more communication channels; and

a plurality of memory units coupled to said processor through said one or more communication channels, wherein each memory unit comprises;

a plurality of memory devices;

a controller configured to be programmed to perform a first function of multiple functions based on a first configuration indication; and

said controller configured to be programmed to perform a second function of said multiple functions based on a second configuration indication;

wherein said controller is configured to respond to said command from said command interface by performing a plurality of data operations comprising a read operation and a write operation based on a corresponding configuration indication and to perform said plurality of data operations on content of said plurality of memory devices.

16. The memory appliance system of claim 15, wherein the configuration indication is one configuration file of a library of multiple configuration files.

17. The memory appliance system of claim 16, wherein said controller is configured by a configuration file to be programmed to perform a search operation.

18. The memory appliance system of claim 16, wherein said controller is configured by a configuration file to be programmed to perform a sort operation.

19. The memory appliance system of claim 16, wherein said controller is configured by a configuration file to be programmed to perform a custom acceleration.

20. The memory appliance system of claim 15, wherein said controller in a corresponding SMC comprises a field programmable gate array.