Power source for memory circuitry

• US 9,881,654 B2
• Filed: 10/07/2015
• Issued: 01/30/2018
• Est. Priority Date: 01/14/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Peng, Wu-Chin, Lee, Chun-Yi, Chen, Ken-Hui, Chang, Kuen-Long, Hung, Chun Hsiung
• Primary Examiner(s): Tran, Anthan
• Application Number:
  US14/877,723
• Publication Number:
  US 20160203846A1
• Time in Patent Office: 846 Days
• Field of Search: 365226, 327538
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

Claims

1. An integrated circuit comprising:

a power supply input pin receiving an off-chip supply voltage having a variable current;

an on-chip power source powered by the off-chip supply voltage and providing a charging current, the on-chip power source including;

a reference current source providing a reference current having a reference current magnitude I_REF; and

a plurality of transistors having at least two different widths, wherein at least a first one of the plurality of transistors is in series with the reference current source, and at least a second one of the plurality of transistors provides the charging current having a peak current magnitude limited by the reference current magnitude scaled by a ratio of the different widths of at least the first and the second ones of the plurality of transistors; and

a memory array; and

a set of one or more circuits coupled to the memory array and comprising a boost capacitor charged by the charging current from the on-chip power source.

2. The integrated circuit of claim 1, wherein the set of one or more circuits includes a charge pump.

3. The integrated circuit of claim 1, wherein the set of one or more circuits includes a charge pump, the charge pump including:

a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality,

wherein the charge pump stages of the plurality include an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor, and wherein the first mentioned boost capacitor is one of the first boost capacitor and the second boost capacitor of one of the charge pump stages in the plurality of serially coupled charge pump stages.

4. The integrated circuit of claim 1, wherein the set of one or more circuits includes a charge pump, the charge pump including:

a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality,

wherein the charge pump stages of the plurality include an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor, and wherein the first mentioned boost capacitor is one of the first boost capacitor and the second boost capacitor of one of the charge pump stages in the plurality of serially coupled charge pump stages,

wherein the on-chip power source provides charging current to at least one of;

(i) the first boost capacitors of the plurality of serially coupled charge pump stages, (ii) the second boost capacitors of the plurality of serially coupled charge pump stages, and (iii) the input node of a first stage, and wherein the first mentioned boost capacitor is one of the first boost capacitor and the second boost capacitor of one of the charge pump stages in the plurality of serially coupled charge pump stages.

5. The integrated circuit of claim 1, wherein the set of one or more circuits includes a charge pump, the charge pump including:

a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality, wherein a particular stage of the charge pump stages includes;

a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage,

a second transistor selectively electrically coupling the input node and a gate of the first transistor,

wherein the particular stage is in a well surrounded by a plurality of well contacts, and

wherein the input node is defined by a first region in the well, the output node is defined by a second region in the well, the first region and the second region on opposite sides of the gate of the first transistor, the first region having a first distance from a nearest one of the plurality of well contacts averaged along a first perimeter of the first region, the second region having a second distance from another nearest one of the plurality of well contacts averaged along a second perimeter of the first region, the second distance shorter than the first distance.

6. The integrated circuit of claim 1, wherein the set of one or more circuits includes a charge pump, the charge pump including:

a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality, wherein a particular stage of the charge pump stages includes;

a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage,

a second transistor selectively electrically coupling the input node and a gate of the first transistor,

wherein the particular stage is in a well surrounded by a plurality of well contacts, and

wherein the input node is defined by a first region in the well, the output node is defined by a plurality of second regions in the well, and the first region is in between the plurality of second regions.

7. The integrated circuit of claim 1, wherein the plurality of transistors includes a third transistor providing a third transistor current having a peak current magnitude limited by the reference current magnitude scaled by a ratio of the different widths of the first and the third transistors of the plurality of transistors.

8. The integrated circuit of claim 1, wherein the on-chip power source includes:

an operational amplifier in a loop from a gate of at least the first one of the plurality of transistors to the reference current source.

9. The integrated circuit of claim 1, wherein the on-chip power source has a nominal output voltage that is independent of the off-chip supply voltage.

10. The integrated circuit of claim 1, wherein the set of one or more circuits includes a capacitive boosting circuit.

11. The integrated circuit of claim 1, wherein the set of one or more circuits includes an output driver.

12. The integrated circuit of claim 1, wherein the set of one or more circuits includes a clock circuit.

13. A method comprising:

receiving, at an integrated circuit, off-chip supply voltage having a variable current via a power supply input pin;

providing, in the integrated circuit, a charging current with an on-chip power source powered by the off-chip supply voltage, wherein the on-chip power source includes;

a reference current source providing a reference current having a reference current magnitude I_REF; and

a plurality of transistors having at least two different widths, wherein at least a first one of the plurality of transistors is in series with the reference current source, and at least a second one of the plurality of transistors provides the charging current having a peak current magnitude limited by the reference current magnitude scaled by a ratio of the different widths of at least the first and the second ones of the plurality of transistors; and

powering, with the charging current from the on-chip power source, a set of one or more circuits on the integrated circuit coupled to a memory array on the integrated circuit, the one or more circuits including a boost capacitor charged by the charging current.

14. The method of claim 13, wherein the set of one or more circuits includes a charge pump.

15. The method of claim 13, wherein the set of one or more circuits includes a charge pump, the charge pump including:

a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality,

wherein the charge pump stages of the plurality include an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor,

wherein the on-chip power source provides charging current to at least one of;

(i) the first boost capacitors of the plurality of charge pump stages, (ii) the second boost capacitors of the plurality of charge pump stages, and (iii) the input node of a first stage, and wherein the first mentioned boost capacitor is one of the first boost capacitor and the second boost capacitor of one of the charge pump stages in the plurality of serially coupled charge pump stages.

16. The method of claim 13, wherein the set of one or more circuits includes a charge pump, the charge pump including:

a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality, wherein a particular stage of the charge pump stages includes;

a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage,

a second transistor selectively electrically coupling the input node and a gate of the first transistor,

wherein the particular stage is in a well surrounded by a plurality of well contacts, and

wherein the input node is defined by a first region in the well, the output node is defined by a second region in the well, the first region and the second region on opposite sides of the gate of the first transistor, the first region having a first distance from a nearest one of the plurality of well contacts averaged along a first perimeter of the first region, the second region having a second distance from another nearest one of the plurality of well contacts averaged along a second perimeter of the first region, the first distance shorter than the second distance.

17. The method of claim 13, wherein the set of one or more circuits includes a charge pump, the charge pump including:

a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality, wherein a particular stage of the charge pump stages includes;

a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage,

a second transistor selectively electrically coupling the input node and a gate of the first transistor,

wherein the particular stage is in a well surrounded by a plurality of well contacts, and

wherein the input node is defined by a first region in the well, the output node is defined by a plurality of second regions in the well, and the first region is in between the plurality of second regions.

18. The method of claim 13, wherein the on-chip power source includes:

an operational amplifier in a loop from a gate of at least the first one of the plurality of transistors to the reference current source.