Power source for memory circuitry
First Claim
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1. An integrated circuit comprising:
- a power supply input pin receiving an off-chip supply voltage having a variable current;
an on-chip power source powered by the off-chip supply voltage and providing a charging current, the on-chip power source including;
a reference current source providing a reference current having a reference current magnitude IREF; and
a plurality of transistors having at least two different widths, wherein at least a first one of the plurality of transistors is in series with the reference current source, and at least a second one of the plurality of transistors provides the charging current having a peak current magnitude limited by the reference current magnitude scaled by a ratio of the different widths of at least the first and the second ones of the plurality of transistors; and
a memory array; and
a set of one or more circuits coupled to the memory array and comprising a boost capacitor charged by the charging current from the on-chip power source.
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Abstract
An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.
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Citations
18 Claims
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1. An integrated circuit comprising:
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a power supply input pin receiving an off-chip supply voltage having a variable current; an on-chip power source powered by the off-chip supply voltage and providing a charging current, the on-chip power source including; a reference current source providing a reference current having a reference current magnitude IREF; and a plurality of transistors having at least two different widths, wherein at least a first one of the plurality of transistors is in series with the reference current source, and at least a second one of the plurality of transistors provides the charging current having a peak current magnitude limited by the reference current magnitude scaled by a ratio of the different widths of at least the first and the second ones of the plurality of transistors; and a memory array; and a set of one or more circuits coupled to the memory array and comprising a boost capacitor charged by the charging current from the on-chip power source. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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receiving, at an integrated circuit, off-chip supply voltage having a variable current via a power supply input pin; providing, in the integrated circuit, a charging current with an on-chip power source powered by the off-chip supply voltage, wherein the on-chip power source includes; a reference current source providing a reference current having a reference current magnitude IREF; and a plurality of transistors having at least two different widths, wherein at least a first one of the plurality of transistors is in series with the reference current source, and at least a second one of the plurality of transistors provides the charging current having a peak current magnitude limited by the reference current magnitude scaled by a ratio of the different widths of at least the first and the second ones of the plurality of transistors; and powering, with the charging current from the on-chip power source, a set of one or more circuits on the integrated circuit coupled to a memory array on the integrated circuit, the one or more circuits including a boost capacitor charged by the charging current. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification