Magnetic memory

• US 9,881,660 B2
• Filed: 09/16/2016
• Issued: 01/30/2018
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoda, Hiroaki, Shimomura, Naoharu, Ohsawa, Yuichi, Daibou, Tadaomi, Inokuchi, Tomoaki, Shirotori, Satoshi, Buyandalai, Altansargai, Kamiguchi, Yuuzo
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US15/267,974
• Publication Number:
  US 20170169872A1
• Time in Patent Office: 501 Days
• Field of Search: 365158, 365171
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A magnetic memory according to an embodiment includes: a conductive layer including a first and second terminals; a plurality of magnetoresistive elements separately disposed on the conductive layer between the first and second terminals, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and a circuit configured to apply a first potential to the reference layers of the magnetoresistive elements and to flow a first write current between the first and second terminals, and configured to apply a second potential to the reference layer or the reference layers of one or more of the magnetoresistive elements to which data is to be written, and to flow a second write current between the first and second terminals in an opposite direction to the first write current.

Claims

1. A magnetic memory comprising:

a conductive layer including a first terminal and a second terminal;

a plurality of magnetoresistive elements separately disposed on the conductive layer between the first terminal and the second terminal, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and

a circuit configured to apply a first potential to the reference layer of at least one first magnetoresistive element among the plurality of the magnetoresistive elements and a second potential that is different from the first potential to the reference layer of at least one second magnetoresistive element that is different from the at least one first magnetoresistive element among the plurality of the magnetoresistive elements and to flow a first write current between the first terminal and the second terminal, and configured to apply the second potential to the reference layer of the at least one first magnetoresistive element and the first potential to the reference layer of the at least one second magnetoresistive element and to flow a second write current between the first terminal and the second terminal in an opposite direction to the first write current.

2. The memory according to claim 1, further comprising:

a plurality of first transistors each corresponding to one of the magnetoresistive elements and including a third terminal, a fourth terminal, and a first control terminal, the third terminal electrically connecting to the reference layer of the corresponding one of the magnetoresistive elements; and

a second transistor including a fifth terminal, a sixth terminal, and second control terminal, the fifth terminal electrically connecting to the first terminal.

3. The memory according to claim 2, wherein the first control terminals of the first transistors electrically connect to different ones of first wirings, and the fourth terminals electrically connect to a second wiring.

4. The memory according to claim 2, further comprising a third transistor including a seventh terminal, an eighth terminal, and a third control terminal, the seventh terminal electrically connecting to the second terminal.

5. The memory according to claim 4, wherein:

the first control terminals of the first transistors electrically connect to different ones of first wirings, and the fourth terminals electrically connect to a second wiring; and

the second control terminal of the second transistor and the third control terminal of the third transistor electrically connect to a third wiring.

6. The memory according to claim 1, further comprising:

a plurality of diodes each corresponding to one of the magnetoresistive elements and including a cathode and an anode, one of the cathode and the anode electrically connecting to the reference layer of the corresponding one of the magnetoresistive elements; and

a first transistor including a third terminal, a fourth terminal, and a first control terminal, the third terminal electrically connecting to the first terminal.

7. The memory according to claim 6, further comprising a second transistor including a fifth terminal, a sixth terminal, and a second control terminal, the fifth terminal electrically connecting to the second terminal.

8. The memory according to claim 7, wherein the first control terminal and the second control terminal electrically connect to a first wiring.

9. The memory according to claim 1, wherein the nonmagnetic layer of the magnetoresistive element is an insulating layer.

10. The memory according to claim 1, wherein the circuit uses a plurality of write pulses to perform a write operation.

11. A magnetic memory comprising:

a first conductive layer including a first terminal and a second terminal;

a first magnetoresistive element and a second magnetoresistive element separately disposed on the first conductive layer between the first terminal and the second terminal, each of the first magnetoresistive element and the second magnetoresistive element including a reference layer, a storage layer between the reference layer and the first conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and

a circuit configured to apply a first potential to the reference layer of the first magnetoresistive element and a second potential that is different from the first potential to the reference layer of the second magnetoresistive element and to flow a first write current between the first terminal and the second terminal, and configured to apply the second potential to the reference layer of the first magnetoresistive element and the first potential to the reference layer of the second magnetoresistive element and to flow a second write current between the first terminal and the second terminal in an opposite direction to the first write current.

12. The memory according to claim 11, wherein:

the conductive layer further includes a third terminal disposed between the first terminal and the second terminal, the first magnetoresistive element and the second magnetoresistive element being disposed between the first terminal and the third terminal;

the magnetic memory further comprises a third magnetoresistive element and a fourth magnetoresistive element separately disposed on the first conductive layer between the second terminal and the third terminal, each of the third magnetoresistive element and the fourth magnetoresistive element including a reference layer, a storage layer between the reference layer and the first conductive layer, and a nonmagnetic layer between the storage layer and the reference layer;

the circuit is configured to apply the first potential to the reference layer of the first magnetoresistive element and the second potential to the reference layer of the second magnetoresistive element and to flow the first write current between the first terminal and the third terminal, and to apply the second potential to the reference layer of the first magnetoresistive element and the first potential to the reference layer of the second magnetoresistive element and to flow the second write current between the first terminal and the third terminal in a write operation to write data to the first magnetoresistive element or the second magnetoresistive element; and

the circuit is configured to apply a third potential to the reference layer of the third magnetoresistive element and a fourth potential that is different from the third potential to the reference layer of the fourth magnetoresistive element and to flow a third write current between the second terminal and the third terminal, and to apply the fourth potential to the reference layer of the third magnetoresistive element and the third potential to the reference layer of the fourth magnetoresistive element and to flow a fourth write current between the second terminal and the third terminal in an opposite direction to the third write current, in a write operation to write data to the third magnetoresistive element or the fourth magnetoresistive element.

13. The memory according to claim 11, further comprising a second conductive layer,

wherein:

the first conductive layer includes a first portion, a second portion, and a third portion, the first portion being disposed between the second portion and the third portion;

the storage layer of the first magnetoresistive element is disposed between the second portion and the nonmagnetic layer of the first magnetoresistive element, and the storage layer of the second magnetoresistive element is disposed between the third portion and the nonmagnetic layer of the second magnetoresistive element; and

the second conductive layer is disposed on the first portion.

14. The memory according to claim 11, further comprising a soft magnetic layer disposed on each of side portions of the first magnetoresistive element and the second magnetoresistive element.

15. The memory according to claim 11, wherein the circuit uses a plurality of write pulses to perform a write operation.

16. The memory according to claim 11, further comprising an electrode, the first conductive layer including a portion located between the first magnetoresistive element and the second magnetoresistive element, the electrode being located on the portion.

17. A magnetic memory comprising:

a conductive layer including a first terminal and a second terminal;

a plurality of magnetoresistive elements separately disposed on the conductive layer between the first terminal and the second terminal, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and

a circuit configured to apply a first potential to the reference layer of at least one first magnetoresistive element among the plurality of the magnetoresistive elements and a second potential that has a polarity different from the first potential to the reference layer of at least one second magnetoresistive element that is different from the at least one first magnetoresistive element among the plurality of the magnetoresistive elements and to flow a first write current between the first terminal and the second terminal, and configured to apply the second potential to the reference layer of the at least one first magnetoresistive element and the first potential to the reference layer of the at least one second magnetoresistive element and to flow a second write current between the first terminal and the second terminal in an opposite direction to the first write current.

18. The memory according to claim 17, further comprising:

a plurality of first transistors each corresponding to one of the magnetoresistive elements and including a third terminal, a fourth terminal, and a first control terminal, the third terminal electrically connecting to the reference layer of the corresponding one of the magnetoresistive elements; and

a second transistor including a fifth terminal, a sixth terminal, and second control terminal, the fifth terminal electrically connecting to the first terminal.

19. The memory according to claim 18, wherein the first control terminals of the first transistors electrically connect to different ones of first wirings, and the fourth terminals electrically connect to a second wiring.

20. The memory according to claim 18, further comprising a third transistor including a seventh terminal, an eighth terminal, and a third control terminal, the seventh terminal electrically connecting to the second terminal.

21. The memory according to claim 20, wherein:

the first control terminals of the first transistors electrically connect to different ones of the first wirings, and the fourth terminals electrically connect to a second wiring; and

the second control terminal of the second transistor and the third control terminal of the third transistor electrically connect to a third wiring.

22. The memory according to claim 17, further comprising:

a plurality of diodes each corresponding to one of the magnetoresistive elements and including a cathode and an anode, one of the cathode and the anode electrically connecting to the reference layer of the corresponding one of the magnetoresistive elements; and

a first transistor including a third terminal, a fourth terminal, and a first control terminal, the third terminal electrically connecting to the first terminal.

23. The memory according to claim 22, further comprising a second transistor including a fifth terminal, a sixth terminal, and a second control terminal, the fifth terminal electrically connecting to the second terminal.

24. The memory according to claim 23, wherein the first control terminal and the second control terminal electrically connect to a first wiring.

25. The memory according to claim 17, wherein the nonmagnetic layer of the magnetoresistive element is an insulating layer.

26. The memory according to claim 17, wherein the circuit uses a plurality of write pulses to perform a write operation.

27. A magnetic memory comprising:

a first conductive layer including a first terminal and a second terminal;

a first magnetoresistive element and a second magnetoresistive element separately disposed on the first conductive layer between the first terminal and the second terminal, each of the first magnetoresistive element and the second magnetoresistive element including a reference layer, a storage layer between the reference layer and the first conductive layer, and a nonmagnetic layer between the storage layer and the reference layer; and

a circuit configured to apply a first potential to the reference layer of the first magnetoresistive element and a second potential that has a polarity different from the first potential to the reference layer of the second magnetoresistive element and to flow a first write current between the first terminal and the second terminal, and configured to apply the second potential to the reference layer of the first magnetoresistive element and the first potential to the reference layer of the second magnetoresistive element and to flow a second write current between the first terminal and the second terminal in an opposite direction to the first write current.

28. The memory according to claim 27, wherein:

the conductive layer further includes a third terminal disposed between the first terminal and the second terminal, the first magnetoresistive element and the second magnetoresistive element being disposed between the first terminal and the third terminal;

the magnetic memory further comprises a third magnetoresistive element and a fourth magnetoresistive element separately disposed on the first conductive layer between the second terminal and the third terminal, each of the third magnetoresistive element and the fourth magnetoresistive element including a reference layer, a storage layer between the reference layer and the first conductive layer, and a nonmagnetic layer between the storage layer and the reference layer;

the circuit is configured to apply the first potential to the reference layer of the first magnetoresistive element and the second potential to the reference layer of the second magnetoresistive element and to flow the first write current between the first terminal and the third terminal, and then to apply the second potential to the reference layer of the first magnetoresistive element and the first potential to the reference layer of the second magnetoresistive element and to flow the second write current between the first terminal and the third terminal in a write operation to write data to the first magnetoresistive element or the second magnetoresistive element; and

the circuit is configured to apply a third potential to the reference layer of the third magnetoresistive element and a fourth potential that is different from the third potential to the reference layer of the fourth magnetoresistive element and to flow a third write current between the second terminal and the third terminal, and then to apply the fourth potential to the reference layer of the third magnetoresistive element and the third potential to the reference layer of the fourth magnetoresistive element and to flow a fourth write current between the second terminal and the third terminal in an opposite direction to the third write current, in a write operation to write data to the third magnetoresistive element or the fourth magnetoresistive element.

29. The memory according to claim 27, further comprising a second conductive layer,

wherein:

the first conductive layer includes a first portion, a second portion, and a third portion, the first portion being disposed between the second portion and the third portion;

the storage layer of the first magnetoresistive element is disposed between the second portion and the nonmagnetic layer of the first magnetoresistive element, and the storage layer of the second magnetoresistive element is disposed between the third portion and the nonmagnetic layer of the second magnetoresistive element; and

the second conductive layer is disposed on the first portion.

30. The memory according to claim 27, further comprising a soft magnetic layer disposed on each of side portions of the first magnetoresistive element and the second magnetoresistive element.

31. The memory according to claim 27, wherein the circuit uses a plurality of write pulses to perform a write operation.

32. The memory according to claim 27, further comprising an electrode, the first conductive layer including a portion located between the first magnetoresistive element and the second magnetoresistive element, the electrode being located on the portion.

33. A magnetic memory comprising:

a conductive layer including a first terminal and a second terminal;

a plurality of magnetoresistive elements separately disposed on the conductive layer between the first terminal and the second terminal, each magnetoresistive element including a reference layer, a storage layer between the reference layer and the conductive layer, and a nonmagnetic layer between the storage layer and the reference layer, each of the plurality of the magnetoresistive elements corresponding to a first group or a second group; and

a circuit configured to apply a first potential to the reference layer of the magnetoresistive element of the first group and a second potential different from the first potential to the reference layer of the magnetoresistive element of the second group and to flow a first write current between the first terminal and the second terminal, and configured to apply the second potential to the reference layer of the magnetoresistive element of the first group and the first potential to the reference layer of the magnetoresistive element of the second group and to flow a second write current between the first terminal and the second terminal in an opposite direction to the first write current.

34. The memory according to claim 33, further comprising:

a plurality of first transistors each corresponding to one of the magnetoresistive elements and including a third terminal, a fourth terminal, and a first control terminal, the third terminal electrically connecting to the reference layer of the corresponding one of the magnetoresistive elements; and

a second transistor including a fifth terminal, a sixth terminal, and second control terminal, the fifth terminal electrically connecting to the first terminal.

35. The memory according to claim 34, wherein the first control terminals of the first transistors electrically connect to different ones of first wirings, and the fourth terminals electrically connect to a second wiring.

36. The memory according to claim 34, further comprising a third transistor including a seventh terminal, an eighth terminal, and a third control terminal, the seventh terminal electrically connecting to the second terminal.

37. The memory according to claim 36, wherein:

the first control terminals of the first transistors electrically connect to different ones of first wirings, and the fourth terminals electrically connect to a second wiring; and

the second control terminal of the second transistor and the third control terminal of the third transistor electrically connect to a third wiring.

38. The memory according to claim 33, further comprising:

a plurality of diodes each corresponding to one of the magnetoresistive elements and including a cathode and an anode, one of the cathode and the anode electrically connecting to the reference layer of the corresponding one of the magnetoresistive elements; and

a first transistor including a third terminal, a fourth terminal, and a first control terminal, the third terminal electrically connecting to the first terminal.

39. The memory according to claim 38, further comprising a second transistor including a fifth terminal, a sixth terminal, and a second control terminal, the fifth terminal electrically connecting to the second terminal.

40. The memory according to claim 39, wherein the first control terminal and the second control terminal electrically connect to a first wiring.

41. The memory according to claim 33, wherein the nonmagnetic layer of the magnetoresistive element is an insulating layer.

42. The memory according to claim 33, wherein the circuit uses a plurality of write pulses to perform a write operation.

43. The memory according to claim 33, wherein the second potential has a polarity different from the first potential.