Wordline driver with integrated voltage level shift function

• US 9,881,669 B1
• Filed: 03/01/2017
• Issued: 01/30/2018
• Est. Priority Date: 03/01/2017
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bringivijayaraghavan, Venkatraghavan, Bhatsoori, Vinay
• Primary Examiner(s): Tran, Anthan
• Application Number:
  US15/446,091
• Time in Patent Office: 335 Days
• Field of Search: 36518523
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Disclosed is a wordline driver with an integrated voltage level shift function. This wordline driver receives a decoder output signal from a wordline address decoder operating at first voltage level. Based on the decoder output signal, it generates and outputs a wordline driving signal, which selectively activates or deactivates a selected wordline. To ensure that the selected wordline, when activated, is at a second voltage level that is higher than the first, the wordline driver uses a combination of clock signals received from multiple timing control blocks operating at the first voltage level and multiple logic gates operating the second voltage level. To ensure that this wordline driving signal remains low during power up when fluctuations occur due to the different voltage levels and, specifically, to ensure that the wordline driving signal only switches to high when it will be stable, the wordline driver can include a reset control block.

Claims

1. A wordline driver comprising:

a first logic gate receiving a first clock signal and a decoder output signal and outputting a first wordline control signal, the first clock signal being received from a first timing control block operating at a first voltage level and the first logic gate operating at a second voltage level that is higher than the first voltage level; and

,

a second logic gate receiving a second clock signal and the first wordline control signal and outputting a second wordline control signal, the second clock signal being inverted relative to the first clock signal and being output from a second timing control block operating at the first voltage level and the second logic gate operating at the second voltage level.

2. The wordline driver of claim 1, the first clock signal having a two-gate delay relative to an initial clock signal and the second clock signal having a three-gate delay relative to the initial clock signal.

3. The wordline driver of claim 1, the decoder output signal being output to the first logic gate from a row address decoder operating at the first voltage level.

4. The wordline driver of claim 1, the second logic gate comprising a NOR gate.

5. The wordline driver of claim 1, further comprising a first inverter and at least one additional inverter connected in series between the second logic gate and a selected wordline, the first inverter and each additional inverter operating at the second voltage level, the first inverter receiving the second wordline control signal from the second logic gate and outputting an inverted wordline control signal and each additional inverter receiving the inverted wordline control signal and outputting a wordline driving signal to the selected wordline.

6. The wordline driver of claim 1, further comprising a reset control block receiving the second wordline control signal and, based on the second wordline control signal, ensuring that the wordline driving signal remains low during power up.

7. The wordline driver of claim 1, the first wordline control signal remaining high whenever the second wordline control signal is low.

8. A wordline driver comprising:

a first logic gate receiving a first clock signal and a decoder output signal and outputting a first wordline control signal, the first clock signal being received from a first timing control block that is electrically connected to a first voltage rail so as to operate at a first voltage level, and the first logic gate being electrically connected to a second voltage rail so as to operate at a second voltage level that is higher than the first voltage level;

a second logic gate receiving a second clock signal and the first wordline control signal and outputting a second wordline control signal, the second clock signal being inverted relative to the first clock signal and being received from a second timing control block that is electrically connected to the first voltage rail so as to operate at the first voltage level, the second logic gate being electrically connected to the second voltage rail so as to operate at the second voltage level, and the second wordline control signal being used to generate a wordline driving signal for activation and deactivation of a selected wordline; and

a reset control block electrically connected to the second voltage rail so as to operate at the second voltage level, the reset control block receiving the second wordline control signal and, based on the second wordline control signal, ensuring that the wordline driving signal remains low during power up.

9. The wordline driver of claim 8, the first clock signal having a two-gate delay relative to an initial clock signal and the second clock signal having a three-gate delay relative to the initial clock signal.

10. The wordline driver of claim 8, the decoder output signal being output to the first logic gate from a row address decoder that is electrically connected to the first voltage rail so as to operate at the first voltage level.

11. The wordline driver of claim 8, the second logic gate comprising a NOR gate.

12. The wordline driver of claim 8, further comprising a first inverter and at least one additional inverter connected in series between the second logic gate and the selected wordline, the first inverter and each additional inverter being electrically connected to the second voltage rail so as to operate at the second voltage level, the first inverter receiving the second wordline control signal from the second logic gate and outputting an inverted wordline control signal and each additional inverter receiving the inverted wordline control signal and outputting the wordline driving signal to the selected wordline.

13. The wordline driver of claim 8, further comprising a p-type field effect transistor electrically connected between the second voltage rail and an output node of the first logic gate, the p-type field effect transistor being controlled by the second wordline control signal.

14. A wordline driver comprising:

a first logic gate receiving a first clock signal and a decoder output signal and outputting a first wordline control signal, the first clock signal being received from a first timing control block that is electrically connected to a first voltage rail so as to operate at a first voltage level and the first logic gate being electrically connected to a second voltage rail so as to operate at a second voltage level that is higher than the first voltage level;

a second logic gate comprising a NOR gate receiving a second clock signal and the first wordline control signal and outputting a second wordline control signal, the second clock signal being inverted relative to the first clock signal and being received from a second timing control block that is electrically connected to the first voltage rail so as to operate at the first voltage level, the second logic gate being electrically connected to the second voltage rail so as to operate at the second voltage level, and the second wordline control signal being used to generate a wordline driving signal for activation and deactivation of a selected wordline; and

a reset control block electrically connected to the second voltage rail so as to operate at the second voltage level, the reset control block receiving the second wordline control signal and, based on the second wordline control signal, ensuring that the wordline driving signal remains low during power up.

15. The wordline driver of claim 14, the first clock signal having a two-gate delay relative to an initial clock signal and the second clock signal having a three-gate delay relative to an initial clock signal.

16. The wordline driver of claim 14, the decoder output signal being output to the first logic gate from a row address decoder that is electrically connected to the first voltage rail so as to operate at the first voltage level.

17. The wordline driver of claim 14, further comprising a first inverter and at least one additional inverter connected in series between the second logic gate and the selected wordline, the first inverter and each additional inverter being electrically connected to the second voltage rail so as to operate at the second voltage level, the first inverter receiving the second wordline control signal from the second logic gate and outputting an inverted wordline control signal and each additional inverter receiving the inverted wordline control signal and outputting the wordline driving signal to the selected wordline.

18. The wordline driver of claim 14,

the first logic gate comprising:

an output node;

a first p-type field effect transistor and a second p-type field effect transistor connected in parallel between the second voltage rail and a third p-type field effect transistor connected to the output node; and

a first n-type field effect transistor and a second n-type field effect transistor connected in series between the output node and ground,

the first p-type field effect transistor and the second n-type field effect transistor being controlled by the first clock signal,

the second p-type field effect transistor and the first n-type field effect transistor being controlled by the decoder output signal,

the third p-type field effect transistor being controlled by a reset control signal, and

the first wordline control signal being output at the output node.

19. The wordline driver of claim 18, the reset control signal controlling the third p-type field effect transistor in order to ensure that the wordline driving signal remains low during power up.

20. The wordline driver of claim 18, the first logic gate further comprising an additional p-type field effect transistor electrically connected between the second p-type field effect transistor and the output node, the additional p-type field effect transistor being controlled by the second wordline control signal.