Nonvolatile memory device, operating method thereof and memory system including the same

• US 9,881,685 B2
• Filed: 03/17/2017
• Issued: 01/30/2018
• Est. Priority Date: 08/26/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Chi Weon, Chae, Donghyuk, Park, Jae-Woo, Nam, Sang-Wan
• Primary Examiner(s): DINH, SON T
• Application Number:
  US15/461,835
• Publication Number:
  US 20170194058A1
• Time in Patent Office: 319 Days
• Field of Search: 36518529, 36518522
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Claims

1. A method of erasing a three dimensional (3D) nonvolatile memory device which includes a first memory cell strings and a second memory cell strings, the first memory cell strings and the second memory cell strings including first memory cells and second memory cells respectively, each of the first and the second memory cells being connected in series and stacked in a direction substantially perpendicular to a substrate, the first memory cell strings being connected to a first string selection line and the second memory cell strings being connected to a second string selection line, at least one of the first memory cells and at least one of the second memory cells being connected to a word line and one of the first memory cell strings and one of the second memory cell strings being connected to a bit-line, the method comprising:

performing a first erasure operation to first memory cells and the second memory cells by applying a first word line erasure voltage on the word line and applying a first erasure voltage to the substrate;

performing a first erasure verification operation to the first memory cells after the performing the first erasure operation by applying a first erasure verification voltage on the word line;

determining whether the first erasure verification passed or failed after the first erasure verification operation; and

if the first erasure verification is determined to be passed, performing a second erasure verification operation to the second memory cells by applying a second erasure verification voltage on the word line, and if the first erasure verification is determined to be failed, performing a second erasure operation to first memory cells and the second memory cells by applying a second word line erasure voltage on the word line and applying a second erasure voltage to the substrate of the first memory cells and the second memory cells.

2. The method of claim 1, wherein the first word line erasure voltage and the second word line erasure voltage are the same positive voltage respectively.

3. The method of claim 1, wherein the first word line erasure voltage and the second word line erasure voltage are positive voltage and have different levels respectively.

4. The method of claim 1, wherein the first word line erasure voltage and the second word line erasure voltage are ground voltage respectively.

5. The method of claim 1, wherein both the first erasure voltage and the second erasure voltage are positive voltages respectively, and the first erasure voltage is smaller than the second erasure voltage.

6. The method of claim 1, wherein the voltage level of the word line is transitioned from the first erasure verification voltage to the second word line erasure voltage before performing the second erasure operation.

7. The method of claim 1, wherein the method further comprising:

determining whether the second erasure verification passed or failed after the second erasure verification operation;

if the second erasure verification is determined to be passed, reporting a completion of the erasure operation for the first memory cells and the second memory cells; and

if the second erasure verification is determined to be failed, comparing a erase count with a predetermined number.

8. The method of claim 7, wherein the method further comprising:

if the erase count is equal to or smaller than the predetermined number, performing a third erasure operation to the first memory cells and the second memory cells by applying a third erasure voltage on the substrate, the third erasure voltage being greater than the second erasure voltage; and

if the erase count is greater than the predetermined number, reporting an erasure error for the first memory cells and the second memory cells.

9. The method of claim 8, wherein the method further comprises counting up the erase count before performing the third erase operation to the first memory cells and the second memory cells.

10. The method of claim 8, wherein the method further comprises determining whether the first erasure verification operation is to be re-performed to the first memory cells after the performing the second erasure operation based on a first pass/fail result of the first erasure verification operation.

11. The method of claim 8, wherein, if the first pass/fail result is a pass, the first erasure verification operation is not to be re-performed to the first memory cells after the performing the second erasure operation.

12. The method of claim 1, wherein the first memory cell strings and the second memory cell strings are connected to a ground selection line.

13. The method of claim 1, wherein the first memory cell strings and the second memory cell strings includes a first string selection transistor and second string selection transistor respectively.

14. The method of claim 13, wherein, during the first erasure verification operation, the first string selection transistor is selected while the second string selection line is disabled.

15. The method of claim 1, wherein the performing the first erasure operation further includes floating a common source line connected to the first memory cell strings and the second memory cell strings during applying a first erase voltage to the substrate.

16. A method of erasing a three dimensional (3D) nonvolatile memory device which includes a first memory cell strings and a second memory cell strings, the first memory cell strings and the second memory cell strings including first memory cells and second memory cells respectively, each of the first and the second memory cells being connected in series and stacked in a direction substantially perpendicular to a substrate, the first memory cell strings being connected to a first string selection line and the second memory cell strings being connected to a second string selection line, at least one of the first memory cells and at least one of the second memory cells being connected to a word line and one of the first memory cell strings and one of the second memory cell strings being connected to a bit-line, the method comprising:

a) performing a first erasure operation to first memory cells and the second memory cells by applying a first word line erasure voltage on the word line and applying a first erasure voltage to the substrate;

b) performing a first erasure verification operation to the first memory cells after the performing the first erasure operation by applying a first erasure verification voltage on the word line;

c) determining whether the first erasure verification passed or failed after the first erasure verification operation; and

if the first erasure verification is determined to be passed, performing a second erasure verification operation to the second memory cells by applying a second erasure verification voltage on the word line, and if the first erasure verification is determined to be failed, adjusting the level of the word line to a ground voltage, and performing a second erasure operation to first memory cells and the second memory cells by applying a second word line erasure voltage on the word line and applying a second erasure voltage to the substrate of the first memory cells and the second memory cells; and

d) repeating steps a) to c) until all erasure verification operation being passed so long as a erase count for the first memory cell strings and the second memory cell strings is equal to or less than a predetermined value.

17. The method of claim 16, wherein the first word line erasure voltage and the second word line erasure voltage are the same positive voltage respectively.

18. The method of claim 16, wherein the first word line erasure voltage and the second word line erasure voltage are positive voltage and have different levels respectively.

19. The method of claim 16, wherein the first word line erasure voltage and the second word line erasure voltage are ground voltage respectively.

20. The method of claim 16, wherein both the first erasure voltage and the second erasure voltage are positive voltages respectively, and the first erasure voltage is smaller than the second erasure voltage.

21. The method of claim 16, wherein the method further comprises reporting a completion of the erasure operation for the first memory cells and the second memory cells if all erasure verification operation pass.

22. The method of claim 16, wherein the method further comprises reporting an erasure error for the first memory cells and the second memory cells if the erase count is greater than the predetermined number.

23. The method of claim 16, wherein the first memory cell strings and the second memory cell strings includes a first string selection transistor and second string selection transistor respectively.

24. The method of claim 16, wherein, during the first erasure verification operation, the first string selection transistor is selected while the second string selection line is disabled.