Schemes for forming barrier layers for copper in interconnect structures

• US 9,881,871 B2
• Filed: 08/31/2015
• Issued: 01/30/2018
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Hai-Ching, Bao, Tien-I
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US14/841,346
• Publication Number:
  US 20150371953A1
• Time in Patent Office: 883 Days
• Field of Search: None
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a first barrier layer within an opening of a dielectric layer;

filling a remainder of the opening with a conductive material;

removing contaminants from the conductive material; and

forming a second barrier layer onto the conductive material by soaking the conductive material in a carbon-containing silane-based chemical, the second barrier layer comprising a silicide throughout the second barrier layer at an end of the soaking the conductive material, wherein the second barrier layer extends over the first barrier layer but does not extend over the dielectric layer.

2. The method of claim 1, wherein the removing the contaminants removes oxygen from the conductive material.

3. The method of claim 1, wherein the removing the contaminants is performed at least in part in a hydrogen-based gas environment.

4. The method of claim 3, wherein the hydrogen-based gas environment comprises hydrogen.

5. The method of claim 3, wherein the hydrogen-based gas environment comprises ammonia.

6. The method of claim 3, wherein the hydrogen-based gas environment comprises methane.

7. The method of claim 1, wherein the removing the contaminants is performed at least in part in a nitrogen-based gas environment.

8. The method of claim 7, wherein the nitrogen-based gas environment comprises nitrogen.

9. A method of manufacturing a semiconductor device, the method comprising:

forming a first barrier layer lining an opening in a dielectric layer, the first barrier layer comprising a first element;

forming a conductive material within the opening, the conductive material comprising a second element different from the first element; and

forming a capping layer over the conductive material and a portion of the first barrier layer in physical contact with a sidewall of the conductive material, at least a portion of the capping layer extending below a topmost surface of the conductive material, the capping layer not extending over the dielectric layer, the forming the capping layer comprising;

forming a first material in physical contact with the conductive material, wherein the first material comprises the second element and a third element different from the first element and the second element; and

forming a second material in physical contact with the first barrier layer, wherein the second material comprises the first element and the third element.

10. The method of claim 9, wherein the third element is silicon.

11. The method of claim 9, wherein the capping layer extends into a recess between the conductive material and the dielectric layer.

12. The method of claim 11, wherein the recess has a first depth of greater than about 50 Å

.

13. The method of claim 11, wherein the recess has a first depth of greater than about 5% of a thickness of the conductive material.

14. The method of claim 9, wherein the first element is cobalt.

15. A method of manufacturing a semiconductor device, the method comprising:

forming a low-k dielectric layer over a substrate;

embedding a conductive wiring in the low-k dielectric layer; and

thermal soaking the conductive wiring in a gas with SiH-bonds, a material of the conductive wiring reacting with the gas with SiH-bonds to form a barrier layer on the conductive wiring, the barrier layer comprising a silicide and having a width larger than a width of the conductive wiring.

16. The method of claim 15, further comprising performing a decontamination process prior to the thermal soaking the conductive wiring.

17. The method of claim 16, wherein the decontamination process is performed at least in part in a hydrogen-based gas environment.

18. The method of claim 16, further comprising passivating the barrier layer after the thermal soaking the conductive wiring.

19. The method of claim 18, wherein the passivating the barrier layer is performed at least in part with a plasma treatment.

20. The method of claim 19, wherein the passivating the barrier layer is performed with a carbon-containing gas.