Semiconductor device and manufacturing method thereof

• US 9,882,013 B2
• Filed: 03/31/2016
• Issued: 01/30/2018
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Jung-Wang, Chang, Kuo Hui, Lin, Mu-Tsang
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US15/086,072
• Publication Number:
  US 20170288032A1
• Time in Patent Office: 670 Days
• Field of Search: 257288
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an angle of a base corner of the gate electrode is greater than 90 degrees. The source and drain regions are located in the substrate at sides of the gate electrode. The spacer is located at a sidewall of the gate electrode.

Claims

1. A semiconductor device, comprising:

a gate electrode, located over a substrate, wherein an angle of a base corner of the gate electrode is greater than 90 degrees;

source and drain regions, located in the substrate at sides of the gate electrode; and

a spacer, located at a sidewall of the gate electrode,

wherein an outer sidewall of the spacer is a vertical surface and is opposite to the sidewall of the gate electrode, and a bottom critical dimension of the spacer is greater than a middle critical dimension of the spacer.

2. The semiconductor device as claimed in claim 1, wherein a bottom critical dimension of the gate electrode is smaller than a middle critical dimension of the gate electrode.

3. The semiconductor device as claimed in claim 2, wherein at least a portion of a lower sidewall of the gate electrode comprises a curved surface or an inclined surface.

4. The semiconductor device as claimed in claim 2, wherein a cross section of a portion of the gate electrode is in a shape of a bowling pin, a rugby ball, or an upside down bell shape.

5. The semiconductor device as claimed in claim 1, wherein there is an increase from the middle critical dimension of the spacer to the bottom critical dimension of the spacer.

6. The semiconductor device as claimed in claim 1, wherein the angle of the base corner is in a range from 95 degrees to 120 degrees.

7. A semiconductor device, comprising:

a gate structure, located over a substrate, wherein the gate structure comprises a wide middle gate electrode;

source and drain regions, located in the substrate at sides of the gate structure; and

a spacer, located at a sidewall of the gate structure, wherein the spacer has a neck region between a top and a bottom of the spacer.

8. The semiconductor device as claimed in claim 7, wherein a location of a middle critical dimension of the wide-middle gate electrode is within a range from ⅖

to ⅗

of a height of the wide-middle gate electrode.

9. The semiconductor device as claimed in claim 7, wherein an undercut is provided between the sidewall of the gate structure and a surface of the substrate, and at least a portion of the spacer is filled into the undercut.

10. The semiconductor device as claimed in claim 7, wherein a bottom critical dimension of the spacer is greater than a middle critical dimension of the spacer.

11. The semiconductor device as claimed in claim 7, wherein there is an increase from a middle critical dimension of the spacer to a bottom critical dimension of the spacer.

12. The semiconductor device as claimed in claim 11, wherein at least a portion of a side surface from the spacer with the middle critical dimension to the spacer with the bottom critical dimension is a curved surface or an inclined surface.

13. A semiconductor device, comprising:

a gate structure, located over a substrate, wherein the gate structure comprises a wide middle gate electrode;

source and drain regions, located in the substrate at sides of the gate structure; and

a spacer, located at a sidewall of the gate structure,

wherein at least a portion of a side surface of the wide middle gate electrode is a curved surface.

14. The semiconductor device as claimed in claim 13, wherein a location of a middle critical dimension of the wide middle gate electrode is within a range from ⅖

to ⅗

of a height of the wide-middle gate electrode.

15. The semiconductor device as claimed in claim 13, wherein an undercut is provided between the sidewall of the gate structure and a surface of the substrate, and at least a portion of the spacer is filled into the undercut.

16. The semiconductor device as claimed in claim 13, wherein a bottom critical dimension of the spacer is greater than a middle critical dimension of the spacer.

17. The semiconductor device as claimed in claim 13, wherein there is an increase from a middle critical dimension of the spacer to a bottom critical dimension of the spacer.

18. The semiconductor device as claimed in claim 13, wherein an angle of a base corner of the wide middle gate electrode is greater than 90 degrees.

19. The semiconductor device as claimed in claim 18, wherein the angle of the base corner is in a range from 95 degrees to 120 degrees.